esp32p4/lp_i2s0/
rx_conf1.rs1#[doc = "Register `RX_CONF1` reader"]
2pub type R = crate::R<RX_CONF1_SPEC>;
3#[doc = "Register `RX_CONF1` writer"]
4pub type W = crate::W<RX_CONF1_SPEC>;
5#[doc = "Field `RX_TDM_WS_WIDTH` reader - The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
6pub type RX_TDM_WS_WIDTH_R = crate::FieldReader;
7#[doc = "Field `RX_TDM_WS_WIDTH` writer - The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
8pub type RX_TDM_WS_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
9#[doc = "Field `RX_BCK_DIV_NUM` reader - Bit clock configuration bits in receiver mode."]
10pub type RX_BCK_DIV_NUM_R = crate::FieldReader;
11#[doc = "Field `RX_BCK_DIV_NUM` writer - Bit clock configuration bits in receiver mode."]
12pub type RX_BCK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13#[doc = "Field `RX_BITS_MOD` reader - Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."]
14pub type RX_BITS_MOD_R = crate::FieldReader;
15#[doc = "Field `RX_BITS_MOD` writer - Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."]
16pub type RX_BITS_MOD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
17#[doc = "Field `RX_HALF_SAMPLE_BITS` reader - I2S Rx half sample bits -1."]
18pub type RX_HALF_SAMPLE_BITS_R = crate::FieldReader;
19#[doc = "Field `RX_HALF_SAMPLE_BITS` writer - I2S Rx half sample bits -1."]
20pub type RX_HALF_SAMPLE_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
21#[doc = "Field `RX_TDM_CHAN_BITS` reader - The Rx bit number for each channel minus 1in TDM mode."]
22pub type RX_TDM_CHAN_BITS_R = crate::FieldReader;
23#[doc = "Field `RX_TDM_CHAN_BITS` writer - The Rx bit number for each channel minus 1in TDM mode."]
24pub type RX_TDM_CHAN_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
25#[doc = "Field `RX_MSB_SHIFT` reader - Set this bit to enable receiver in Phillips standard mode"]
26pub type RX_MSB_SHIFT_R = crate::BitReader;
27#[doc = "Field `RX_MSB_SHIFT` writer - Set this bit to enable receiver in Phillips standard mode"]
28pub type RX_MSB_SHIFT_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30 #[doc = "Bits 0:6 - The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
31 #[inline(always)]
32 pub fn rx_tdm_ws_width(&self) -> RX_TDM_WS_WIDTH_R {
33 RX_TDM_WS_WIDTH_R::new((self.bits & 0x7f) as u8)
34 }
35 #[doc = "Bits 7:12 - Bit clock configuration bits in receiver mode."]
36 #[inline(always)]
37 pub fn rx_bck_div_num(&self) -> RX_BCK_DIV_NUM_R {
38 RX_BCK_DIV_NUM_R::new(((self.bits >> 7) & 0x3f) as u8)
39 }
40 #[doc = "Bits 13:17 - Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."]
41 #[inline(always)]
42 pub fn rx_bits_mod(&self) -> RX_BITS_MOD_R {
43 RX_BITS_MOD_R::new(((self.bits >> 13) & 0x1f) as u8)
44 }
45 #[doc = "Bits 18:23 - I2S Rx half sample bits -1."]
46 #[inline(always)]
47 pub fn rx_half_sample_bits(&self) -> RX_HALF_SAMPLE_BITS_R {
48 RX_HALF_SAMPLE_BITS_R::new(((self.bits >> 18) & 0x3f) as u8)
49 }
50 #[doc = "Bits 24:28 - The Rx bit number for each channel minus 1in TDM mode."]
51 #[inline(always)]
52 pub fn rx_tdm_chan_bits(&self) -> RX_TDM_CHAN_BITS_R {
53 RX_TDM_CHAN_BITS_R::new(((self.bits >> 24) & 0x1f) as u8)
54 }
55 #[doc = "Bit 29 - Set this bit to enable receiver in Phillips standard mode"]
56 #[inline(always)]
57 pub fn rx_msb_shift(&self) -> RX_MSB_SHIFT_R {
58 RX_MSB_SHIFT_R::new(((self.bits >> 29) & 1) != 0)
59 }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64 f.debug_struct("RX_CONF1")
65 .field(
66 "rx_tdm_ws_width",
67 &format_args!("{}", self.rx_tdm_ws_width().bits()),
68 )
69 .field(
70 "rx_bck_div_num",
71 &format_args!("{}", self.rx_bck_div_num().bits()),
72 )
73 .field(
74 "rx_bits_mod",
75 &format_args!("{}", self.rx_bits_mod().bits()),
76 )
77 .field(
78 "rx_half_sample_bits",
79 &format_args!("{}", self.rx_half_sample_bits().bits()),
80 )
81 .field(
82 "rx_tdm_chan_bits",
83 &format_args!("{}", self.rx_tdm_chan_bits().bits()),
84 )
85 .field(
86 "rx_msb_shift",
87 &format_args!("{}", self.rx_msb_shift().bit()),
88 )
89 .finish()
90 }
91}
92#[cfg(feature = "impl-register-debug")]
93impl core::fmt::Debug for crate::generic::Reg<RX_CONF1_SPEC> {
94 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
95 core::fmt::Debug::fmt(&self.read(), f)
96 }
97}
98impl W {
99 #[doc = "Bits 0:6 - The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
100 #[inline(always)]
101 #[must_use]
102 pub fn rx_tdm_ws_width(&mut self) -> RX_TDM_WS_WIDTH_W<RX_CONF1_SPEC> {
103 RX_TDM_WS_WIDTH_W::new(self, 0)
104 }
105 #[doc = "Bits 7:12 - Bit clock configuration bits in receiver mode."]
106 #[inline(always)]
107 #[must_use]
108 pub fn rx_bck_div_num(&mut self) -> RX_BCK_DIV_NUM_W<RX_CONF1_SPEC> {
109 RX_BCK_DIV_NUM_W::new(self, 7)
110 }
111 #[doc = "Bits 13:17 - Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."]
112 #[inline(always)]
113 #[must_use]
114 pub fn rx_bits_mod(&mut self) -> RX_BITS_MOD_W<RX_CONF1_SPEC> {
115 RX_BITS_MOD_W::new(self, 13)
116 }
117 #[doc = "Bits 18:23 - I2S Rx half sample bits -1."]
118 #[inline(always)]
119 #[must_use]
120 pub fn rx_half_sample_bits(&mut self) -> RX_HALF_SAMPLE_BITS_W<RX_CONF1_SPEC> {
121 RX_HALF_SAMPLE_BITS_W::new(self, 18)
122 }
123 #[doc = "Bits 24:28 - The Rx bit number for each channel minus 1in TDM mode."]
124 #[inline(always)]
125 #[must_use]
126 pub fn rx_tdm_chan_bits(&mut self) -> RX_TDM_CHAN_BITS_W<RX_CONF1_SPEC> {
127 RX_TDM_CHAN_BITS_W::new(self, 24)
128 }
129 #[doc = "Bit 29 - Set this bit to enable receiver in Phillips standard mode"]
130 #[inline(always)]
131 #[must_use]
132 pub fn rx_msb_shift(&mut self) -> RX_MSB_SHIFT_W<RX_CONF1_SPEC> {
133 RX_MSB_SHIFT_W::new(self, 29)
134 }
135}
136#[doc = "I2S RX configure register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
137pub struct RX_CONF1_SPEC;
138impl crate::RegisterSpec for RX_CONF1_SPEC {
139 type Ux = u32;
140}
141#[doc = "`read()` method returns [`rx_conf1::R`](R) reader structure"]
142impl crate::Readable for RX_CONF1_SPEC {}
143#[doc = "`write(|w| ..)` method takes [`rx_conf1::W`](W) writer structure"]
144impl crate::Writable for RX_CONF1_SPEC {
145 type Safety = crate::Unsafe;
146 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
147 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
148}
149#[doc = "`reset()` method sets RX_CONF1 to value 0x2f3d_e300"]
150impl crate::Resettable for RX_CONF1_SPEC {
151 const RESET_VALUE: u32 = 0x2f3d_e300;
152}