esp32p4/lp_i2c0/
sr.rs

1#[doc = "Register `SR` reader"]
2pub type R = crate::R<SR_SPEC>;
3#[doc = "Field `RESP_REC` reader - Represents the received ACK value in master mode or slave mode. 0: ACK, 1: NACK."]
4pub type RESP_REC_R = crate::BitReader;
5#[doc = "Field `ARB_LOST` reader - Represents whether the I2C controller loses control of SCL line. 0: No arbitration lost 1: Arbitration lost"]
6pub type ARB_LOST_R = crate::BitReader;
7#[doc = "Field `BUS_BUSY` reader - Represents the I2C bus state. 1: The I2C bus is busy transferring data, 0: The I2C bus is in idle state."]
8pub type BUS_BUSY_R = crate::BitReader;
9#[doc = "Field `RXFIFO_CNT` reader - Represents the number of data bytes to be sent."]
10pub type RXFIFO_CNT_R = crate::FieldReader;
11#[doc = "Field `TXFIFO_CNT` reader - Represents the number of data bytes received in RAM."]
12pub type TXFIFO_CNT_R = crate::FieldReader;
13#[doc = "Field `SCL_MAIN_STATE_LAST` reader - Represents the states of the I2C module state machine. 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK"]
14pub type SCL_MAIN_STATE_LAST_R = crate::FieldReader;
15#[doc = "Field `SCL_STATE_LAST` reader - Represents the states of the state machine used to produce SCL. 0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop"]
16pub type SCL_STATE_LAST_R = crate::FieldReader;
17impl R {
18    #[doc = "Bit 0 - Represents the received ACK value in master mode or slave mode. 0: ACK, 1: NACK."]
19    #[inline(always)]
20    pub fn resp_rec(&self) -> RESP_REC_R {
21        RESP_REC_R::new((self.bits & 1) != 0)
22    }
23    #[doc = "Bit 3 - Represents whether the I2C controller loses control of SCL line. 0: No arbitration lost 1: Arbitration lost"]
24    #[inline(always)]
25    pub fn arb_lost(&self) -> ARB_LOST_R {
26        ARB_LOST_R::new(((self.bits >> 3) & 1) != 0)
27    }
28    #[doc = "Bit 4 - Represents the I2C bus state. 1: The I2C bus is busy transferring data, 0: The I2C bus is in idle state."]
29    #[inline(always)]
30    pub fn bus_busy(&self) -> BUS_BUSY_R {
31        BUS_BUSY_R::new(((self.bits >> 4) & 1) != 0)
32    }
33    #[doc = "Bits 8:12 - Represents the number of data bytes to be sent."]
34    #[inline(always)]
35    pub fn rxfifo_cnt(&self) -> RXFIFO_CNT_R {
36        RXFIFO_CNT_R::new(((self.bits >> 8) & 0x1f) as u8)
37    }
38    #[doc = "Bits 18:22 - Represents the number of data bytes received in RAM."]
39    #[inline(always)]
40    pub fn txfifo_cnt(&self) -> TXFIFO_CNT_R {
41        TXFIFO_CNT_R::new(((self.bits >> 18) & 0x1f) as u8)
42    }
43    #[doc = "Bits 24:26 - Represents the states of the I2C module state machine. 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK"]
44    #[inline(always)]
45    pub fn scl_main_state_last(&self) -> SCL_MAIN_STATE_LAST_R {
46        SCL_MAIN_STATE_LAST_R::new(((self.bits >> 24) & 7) as u8)
47    }
48    #[doc = "Bits 28:30 - Represents the states of the state machine used to produce SCL. 0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop"]
49    #[inline(always)]
50    pub fn scl_state_last(&self) -> SCL_STATE_LAST_R {
51        SCL_STATE_LAST_R::new(((self.bits >> 28) & 7) as u8)
52    }
53}
54#[cfg(feature = "impl-register-debug")]
55impl core::fmt::Debug for R {
56    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
57        f.debug_struct("SR")
58            .field("resp_rec", &format_args!("{}", self.resp_rec().bit()))
59            .field("arb_lost", &format_args!("{}", self.arb_lost().bit()))
60            .field("bus_busy", &format_args!("{}", self.bus_busy().bit()))
61            .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits()))
62            .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits()))
63            .field(
64                "scl_main_state_last",
65                &format_args!("{}", self.scl_main_state_last().bits()),
66            )
67            .field(
68                "scl_state_last",
69                &format_args!("{}", self.scl_state_last().bits()),
70            )
71            .finish()
72    }
73}
74#[cfg(feature = "impl-register-debug")]
75impl core::fmt::Debug for crate::generic::Reg<SR_SPEC> {
76    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
77        core::fmt::Debug::fmt(&self.read(), f)
78    }
79}
80#[doc = "Describe I2C work status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
81pub struct SR_SPEC;
82impl crate::RegisterSpec for SR_SPEC {
83    type Ux = u32;
84}
85#[doc = "`read()` method returns [`sr::R`](R) reader structure"]
86impl crate::Readable for SR_SPEC {}
87#[doc = "`reset()` method sets SR to value 0"]
88impl crate::Resettable for SR_SPEC {
89    const RESET_VALUE: u32 = 0;
90}
esp32p4/lp_i2c0/sr.rs

esp32p4/lp_i2c0/
sr.rs
