esp32p4/ledc/timer/
conf.rs

1#[doc = "Register `CONF` reader"]
2pub type R = crate::R<CONF_SPEC>;
3#[doc = "Register `CONF` writer"]
4pub type W = crate::W<CONF_SPEC>;
5#[doc = "Field `DUTY_RES` reader - Configures the range of the counter in timer %s."]
6pub type DUTY_RES_R = crate::FieldReader;
7#[doc = "Field `DUTY_RES` writer - Configures the range of the counter in timer %s."]
8pub type DUTY_RES_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `CLK_DIV` reader - Configures the divisor for the divider in timer %s.The least significant eight bits represent the fractional part."]
10pub type CLK_DIV_R = crate::FieldReader<u32>;
11#[doc = "Field `CLK_DIV` writer - Configures the divisor for the divider in timer %s.The least significant eight bits represent the fractional part."]
12pub type CLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>;
13#[doc = "Field `PAUSE` reader - Configures whether or not to pause the counter in timer %s.\\\\0: Normal\\\\1: Pause"]
14pub type PAUSE_R = crate::BitReader;
15#[doc = "Field `PAUSE` writer - Configures whether or not to pause the counter in timer %s.\\\\0: Normal\\\\1: Pause"]
16pub type PAUSE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RST` reader - Configures whether or not to reset timer %s. The counter will show 0 after reset.\\\\0: Not reset\\\\1: Reset"]
18pub type RST_R = crate::BitReader;
19#[doc = "Field `RST` writer - Configures whether or not to reset timer %s. The counter will show 0 after reset.\\\\0: Not reset\\\\1: Reset"]
20pub type RST_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TICK_SEL` reader - Configures which clock is timer %s selected. Unused."]
22pub type TICK_SEL_R = crate::BitReader;
23#[doc = "Field `TICK_SEL` writer - Configures which clock is timer %s selected. Unused."]
24pub type TICK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `PARA_UP` writer - Configures whether or not to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES.\\\\0: Invalid. No effect\\\\1: Update"]
26pub type PARA_UP_W<'a, REG> = crate::BitWriter<'a, REG>;
27impl R {
28    #[doc = "Bits 0:4 - Configures the range of the counter in timer %s."]
29    #[inline(always)]
30    pub fn duty_res(&self) -> DUTY_RES_R {
31        DUTY_RES_R::new((self.bits & 0x1f) as u8)
32    }
33    #[doc = "Bits 5:22 - Configures the divisor for the divider in timer %s.The least significant eight bits represent the fractional part."]
34    #[inline(always)]
35    pub fn clk_div(&self) -> CLK_DIV_R {
36        CLK_DIV_R::new((self.bits >> 5) & 0x0003_ffff)
37    }
38    #[doc = "Bit 23 - Configures whether or not to pause the counter in timer %s.\\\\0: Normal\\\\1: Pause"]
39    #[inline(always)]
40    pub fn pause(&self) -> PAUSE_R {
41        PAUSE_R::new(((self.bits >> 23) & 1) != 0)
42    }
43    #[doc = "Bit 24 - Configures whether or not to reset timer %s. The counter will show 0 after reset.\\\\0: Not reset\\\\1: Reset"]
44    #[inline(always)]
45    pub fn rst(&self) -> RST_R {
46        RST_R::new(((self.bits >> 24) & 1) != 0)
47    }
48    #[doc = "Bit 25 - Configures which clock is timer %s selected. Unused."]
49    #[inline(always)]
50    pub fn tick_sel(&self) -> TICK_SEL_R {
51        TICK_SEL_R::new(((self.bits >> 25) & 1) != 0)
52    }
53}
54#[cfg(feature = "impl-register-debug")]
55impl core::fmt::Debug for R {
56    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
57        f.debug_struct("CONF")
58            .field("duty_res", &format_args!("{}", self.duty_res().bits()))
59            .field("clk_div", &format_args!("{}", self.clk_div().bits()))
60            .field("pause", &format_args!("{}", self.pause().bit()))
61            .field("rst", &format_args!("{}", self.rst().bit()))
62            .field("tick_sel", &format_args!("{}", self.tick_sel().bit()))
63            .finish()
64    }
65}
66#[cfg(feature = "impl-register-debug")]
67impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
68    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
69        core::fmt::Debug::fmt(&self.read(), f)
70    }
71}
72impl W {
73    #[doc = "Bits 0:4 - Configures the range of the counter in timer %s."]
74    #[inline(always)]
75    #[must_use]
76    pub fn duty_res(&mut self) -> DUTY_RES_W<CONF_SPEC> {
77        DUTY_RES_W::new(self, 0)
78    }
79    #[doc = "Bits 5:22 - Configures the divisor for the divider in timer %s.The least significant eight bits represent the fractional part."]
80    #[inline(always)]
81    #[must_use]
82    pub fn clk_div(&mut self) -> CLK_DIV_W<CONF_SPEC> {
83        CLK_DIV_W::new(self, 5)
84    }
85    #[doc = "Bit 23 - Configures whether or not to pause the counter in timer %s.\\\\0: Normal\\\\1: Pause"]
86    #[inline(always)]
87    #[must_use]
88    pub fn pause(&mut self) -> PAUSE_W<CONF_SPEC> {
89        PAUSE_W::new(self, 23)
90    }
91    #[doc = "Bit 24 - Configures whether or not to reset timer %s. The counter will show 0 after reset.\\\\0: Not reset\\\\1: Reset"]
92    #[inline(always)]
93    #[must_use]
94    pub fn rst(&mut self) -> RST_W<CONF_SPEC> {
95        RST_W::new(self, 24)
96    }
97    #[doc = "Bit 25 - Configures which clock is timer %s selected. Unused."]
98    #[inline(always)]
99    #[must_use]
100    pub fn tick_sel(&mut self) -> TICK_SEL_W<CONF_SPEC> {
101        TICK_SEL_W::new(self, 25)
102    }
103    #[doc = "Bit 26 - Configures whether or not to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES.\\\\0: Invalid. No effect\\\\1: Update"]
104    #[inline(always)]
105    #[must_use]
106    pub fn para_up(&mut self) -> PARA_UP_W<CONF_SPEC> {
107        PARA_UP_W::new(self, 26)
108    }
109}
110#[doc = "Timer 0 configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
111pub struct CONF_SPEC;
112impl crate::RegisterSpec for CONF_SPEC {
113    type Ux = u32;
114}
115#[doc = "`read()` method returns [`conf::R`](R) reader structure"]
116impl crate::Readable for CONF_SPEC {}
117#[doc = "`write(|w| ..)` method takes [`conf::W`](W) writer structure"]
118impl crate::Writable for CONF_SPEC {
119    type Safety = crate::Unsafe;
120    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
121    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
122}
123#[doc = "`reset()` method sets CONF to value 0x0100_0000"]
124impl crate::Resettable for CONF_SPEC {
125    const RESET_VALUE: u32 = 0x0100_0000;
126}
esp32p4/ledc/timer/conf.rs

esp32p4/ledc/timer/
conf.rs
