1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `TIMER_OVF(0-3)` writer - Set this bit to clear the TIMER%s_OVF interrupt."]
4pub type TIMER_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `DUTY_CHNG_END_CH(0-7)` writer - Set this bit to clear the DUTY_CHNG_END_CH%s interrupt."]
6pub type DUTY_CHNG_END_CH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `OVF_CNT_CH(0-7)` writer - Set this bit to clear the OVF_CNT_CH%s interrupt."]
8pub type OVF_CNT_CH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[cfg(feature = "impl-register-debug")]
10impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
11 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
12 write!(f, "(not readable)")
13 }
14}
15impl W {
16 #[doc = "Set this bit to clear the TIMER(0-3)_OVF interrupt."]
17 #[doc = ""]
18 #[doc = "NOTE: `n` is number of field in register. `n == 0` corresponds to `TIMER0_OVF` field"]
19 #[inline(always)]
20 #[must_use]
21 pub fn timer_ovf(&mut self, n: u8) -> TIMER_OVF_W<INT_CLR_SPEC> {
22 #[allow(clippy::no_effect)]
23 [(); 4][n as usize];
24 TIMER_OVF_W::new(self, n)
25 }
26 #[doc = "Bit 0 - Set this bit to clear the TIMER0_OVF interrupt."]
27 #[inline(always)]
28 #[must_use]
29 pub fn timer0_ovf(&mut self) -> TIMER_OVF_W<INT_CLR_SPEC> {
30 TIMER_OVF_W::new(self, 0)
31 }
32 #[doc = "Bit 1 - Set this bit to clear the TIMER1_OVF interrupt."]
33 #[inline(always)]
34 #[must_use]
35 pub fn timer1_ovf(&mut self) -> TIMER_OVF_W<INT_CLR_SPEC> {
36 TIMER_OVF_W::new(self, 1)
37 }
38 #[doc = "Bit 2 - Set this bit to clear the TIMER2_OVF interrupt."]
39 #[inline(always)]
40 #[must_use]
41 pub fn timer2_ovf(&mut self) -> TIMER_OVF_W<INT_CLR_SPEC> {
42 TIMER_OVF_W::new(self, 2)
43 }
44 #[doc = "Bit 3 - Set this bit to clear the TIMER3_OVF interrupt."]
45 #[inline(always)]
46 #[must_use]
47 pub fn timer3_ovf(&mut self) -> TIMER_OVF_W<INT_CLR_SPEC> {
48 TIMER_OVF_W::new(self, 3)
49 }
50 #[doc = "Set this bit to clear the DUTY_CHNG_END_CH(0-7) interrupt."]
51 #[doc = ""]
52 #[doc = "NOTE: `n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_CH0` field"]
53 #[inline(always)]
54 #[must_use]
55 pub fn duty_chng_end_ch(&mut self, n: u8) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
56 #[allow(clippy::no_effect)]
57 [(); 8][n as usize];
58 DUTY_CHNG_END_CH_W::new(self, n + 4)
59 }
60 #[doc = "Bit 4 - Set this bit to clear the DUTY_CHNG_END_CH0 interrupt."]
61 #[inline(always)]
62 #[must_use]
63 pub fn duty_chng_end_ch0(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
64 DUTY_CHNG_END_CH_W::new(self, 4)
65 }
66 #[doc = "Bit 5 - Set this bit to clear the DUTY_CHNG_END_CH1 interrupt."]
67 #[inline(always)]
68 #[must_use]
69 pub fn duty_chng_end_ch1(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
70 DUTY_CHNG_END_CH_W::new(self, 5)
71 }
72 #[doc = "Bit 6 - Set this bit to clear the DUTY_CHNG_END_CH2 interrupt."]
73 #[inline(always)]
74 #[must_use]
75 pub fn duty_chng_end_ch2(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
76 DUTY_CHNG_END_CH_W::new(self, 6)
77 }
78 #[doc = "Bit 7 - Set this bit to clear the DUTY_CHNG_END_CH3 interrupt."]
79 #[inline(always)]
80 #[must_use]
81 pub fn duty_chng_end_ch3(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
82 DUTY_CHNG_END_CH_W::new(self, 7)
83 }
84 #[doc = "Bit 8 - Set this bit to clear the DUTY_CHNG_END_CH4 interrupt."]
85 #[inline(always)]
86 #[must_use]
87 pub fn duty_chng_end_ch4(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
88 DUTY_CHNG_END_CH_W::new(self, 8)
89 }
90 #[doc = "Bit 9 - Set this bit to clear the DUTY_CHNG_END_CH5 interrupt."]
91 #[inline(always)]
92 #[must_use]
93 pub fn duty_chng_end_ch5(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
94 DUTY_CHNG_END_CH_W::new(self, 9)
95 }
96 #[doc = "Bit 10 - Set this bit to clear the DUTY_CHNG_END_CH6 interrupt."]
97 #[inline(always)]
98 #[must_use]
99 pub fn duty_chng_end_ch6(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
100 DUTY_CHNG_END_CH_W::new(self, 10)
101 }
102 #[doc = "Bit 11 - Set this bit to clear the DUTY_CHNG_END_CH7 interrupt."]
103 #[inline(always)]
104 #[must_use]
105 pub fn duty_chng_end_ch7(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
106 DUTY_CHNG_END_CH_W::new(self, 11)
107 }
108 #[doc = "Set this bit to clear the OVF_CNT_CH(0-7) interrupt."]
109 #[doc = ""]
110 #[doc = "NOTE: `n` is number of field in register. `n == 0` corresponds to `OVF_CNT_CH0` field"]
111 #[inline(always)]
112 #[must_use]
113 pub fn ovf_cnt_ch(&mut self, n: u8) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
114 #[allow(clippy::no_effect)]
115 [(); 8][n as usize];
116 OVF_CNT_CH_W::new(self, n + 12)
117 }
118 #[doc = "Bit 12 - Set this bit to clear the OVF_CNT_CH0 interrupt."]
119 #[inline(always)]
120 #[must_use]
121 pub fn ovf_cnt_ch0(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
122 OVF_CNT_CH_W::new(self, 12)
123 }
124 #[doc = "Bit 13 - Set this bit to clear the OVF_CNT_CH1 interrupt."]
125 #[inline(always)]
126 #[must_use]
127 pub fn ovf_cnt_ch1(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
128 OVF_CNT_CH_W::new(self, 13)
129 }
130 #[doc = "Bit 14 - Set this bit to clear the OVF_CNT_CH2 interrupt."]
131 #[inline(always)]
132 #[must_use]
133 pub fn ovf_cnt_ch2(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
134 OVF_CNT_CH_W::new(self, 14)
135 }
136 #[doc = "Bit 15 - Set this bit to clear the OVF_CNT_CH3 interrupt."]
137 #[inline(always)]
138 #[must_use]
139 pub fn ovf_cnt_ch3(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
140 OVF_CNT_CH_W::new(self, 15)
141 }
142 #[doc = "Bit 16 - Set this bit to clear the OVF_CNT_CH4 interrupt."]
143 #[inline(always)]
144 #[must_use]
145 pub fn ovf_cnt_ch4(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
146 OVF_CNT_CH_W::new(self, 16)
147 }
148 #[doc = "Bit 17 - Set this bit to clear the OVF_CNT_CH5 interrupt."]
149 #[inline(always)]
150 #[must_use]
151 pub fn ovf_cnt_ch5(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
152 OVF_CNT_CH_W::new(self, 17)
153 }
154 #[doc = "Bit 18 - Set this bit to clear the OVF_CNT_CH6 interrupt."]
155 #[inline(always)]
156 #[must_use]
157 pub fn ovf_cnt_ch6(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
158 OVF_CNT_CH_W::new(self, 18)
159 }
160 #[doc = "Bit 19 - Set this bit to clear the OVF_CNT_CH7 interrupt."]
161 #[inline(always)]
162 #[must_use]
163 pub fn ovf_cnt_ch7(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
164 OVF_CNT_CH_W::new(self, 19)
165 }
166}
167#[doc = "Interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
168pub struct INT_CLR_SPEC;
169impl crate::RegisterSpec for INT_CLR_SPEC {
170 type Ux = u32;
171}
172#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
173impl crate::Writable for INT_CLR_SPEC {
174 type Safety = crate::Unsafe;
175 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
176 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x1011;
177}
178#[doc = "`reset()` method sets INT_CLR to value 0"]
179impl crate::Resettable for INT_CLR_SPEC {
180 const RESET_VALUE: u32 = 0;
181}