1#[doc = "Register `INT_ENA` reader"]
2pub type R = crate::R<INT_ENA_SPEC>;
3#[doc = "Register `INT_ENA` writer"]
4pub type W = crate::W<INT_ENA_SPEC>;
5#[doc = "Field `ISP_DATA_TYPE_ERR_INT_ENA` reader - write 1 to enable input data type error"]
6pub type ISP_DATA_TYPE_ERR_INT_ENA_R = crate::BitReader;
7#[doc = "Field `ISP_DATA_TYPE_ERR_INT_ENA` writer - write 1 to enable input data type error"]
8pub type ISP_DATA_TYPE_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ISP_ASYNC_FIFO_OVF_INT_ENA` reader - write 1 to enable isp input fifo overflow"]
10pub type ISP_ASYNC_FIFO_OVF_INT_ENA_R = crate::BitReader;
11#[doc = "Field `ISP_ASYNC_FIFO_OVF_INT_ENA` writer - write 1 to enable isp input fifo overflow"]
12pub type ISP_ASYNC_FIFO_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `ISP_BUF_FULL_INT_ENA` reader - write 1 to enable isp input buffer full"]
14pub type ISP_BUF_FULL_INT_ENA_R = crate::BitReader;
15#[doc = "Field `ISP_BUF_FULL_INT_ENA` writer - write 1 to enable isp input buffer full"]
16pub type ISP_BUF_FULL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `ISP_HVNUM_SETTING_ERR_INT_ENA` reader - write 1 to enable hnum and vnum setting format error"]
18pub type ISP_HVNUM_SETTING_ERR_INT_ENA_R = crate::BitReader;
19#[doc = "Field `ISP_HVNUM_SETTING_ERR_INT_ENA` writer - write 1 to enable hnum and vnum setting format error"]
20pub type ISP_HVNUM_SETTING_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `ISP_DATA_TYPE_SETTING_ERR_INT_ENA` reader - write 1 to enable setting invalid reg_data_type"]
22pub type ISP_DATA_TYPE_SETTING_ERR_INT_ENA_R = crate::BitReader;
23#[doc = "Field `ISP_DATA_TYPE_SETTING_ERR_INT_ENA` writer - write 1 to enable setting invalid reg_data_type"]
24pub type ISP_DATA_TYPE_SETTING_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `ISP_MIPI_HNUM_UNMATCH_INT_ENA` reader - write 1 to enable hnum setting unmatch with mipi input"]
26pub type ISP_MIPI_HNUM_UNMATCH_INT_ENA_R = crate::BitReader;
27#[doc = "Field `ISP_MIPI_HNUM_UNMATCH_INT_ENA` writer - write 1 to enable hnum setting unmatch with mipi input"]
28pub type ISP_MIPI_HNUM_UNMATCH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `DPC_CHECK_DONE_INT_ENA` reader - write 1 to enable dpc check done"]
30pub type DPC_CHECK_DONE_INT_ENA_R = crate::BitReader;
31#[doc = "Field `DPC_CHECK_DONE_INT_ENA` writer - write 1 to enable dpc check done"]
32pub type DPC_CHECK_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `GAMMA_XCOORD_ERR_INT_ENA` reader - write 1 to enable gamma setting error"]
34pub type GAMMA_XCOORD_ERR_INT_ENA_R = crate::BitReader;
35#[doc = "Field `GAMMA_XCOORD_ERR_INT_ENA` writer - write 1 to enable gamma setting error"]
36pub type GAMMA_XCOORD_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `AE_MONITOR_INT_ENA` reader - write 1 to enable ae monitor"]
38pub type AE_MONITOR_INT_ENA_R = crate::BitReader;
39#[doc = "Field `AE_MONITOR_INT_ENA` writer - write 1 to enable ae monitor"]
40pub type AE_MONITOR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `AE_FRAME_DONE_INT_ENA` reader - write 1 to enable ae"]
42pub type AE_FRAME_DONE_INT_ENA_R = crate::BitReader;
43#[doc = "Field `AE_FRAME_DONE_INT_ENA` writer - write 1 to enable ae"]
44pub type AE_FRAME_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `AF_FDONE_INT_ENA` reader - write 1 to enable af statistic"]
46pub type AF_FDONE_INT_ENA_R = crate::BitReader;
47#[doc = "Field `AF_FDONE_INT_ENA` writer - write 1 to enable af statistic"]
48pub type AF_FDONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `AF_ENV_INT_ENA` reader - write 1 to enable af monitor"]
50pub type AF_ENV_INT_ENA_R = crate::BitReader;
51#[doc = "Field `AF_ENV_INT_ENA` writer - write 1 to enable af monitor"]
52pub type AF_ENV_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `AWB_FDONE_INT_ENA` reader - write 1 to enable awb"]
54pub type AWB_FDONE_INT_ENA_R = crate::BitReader;
55#[doc = "Field `AWB_FDONE_INT_ENA` writer - write 1 to enable awb"]
56pub type AWB_FDONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `HIST_FDONE_INT_ENA` reader - write 1 to enable histogram"]
58pub type HIST_FDONE_INT_ENA_R = crate::BitReader;
59#[doc = "Field `HIST_FDONE_INT_ENA` writer - write 1 to enable histogram"]
60pub type HIST_FDONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `FRAME_INT_ENA` reader - write 1 to enable isp frame end"]
62pub type FRAME_INT_ENA_R = crate::BitReader;
63#[doc = "Field `FRAME_INT_ENA` writer - write 1 to enable isp frame end"]
64pub type FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `BLC_FRAME_INT_ENA` reader - write 1 to enable blc frame done"]
66pub type BLC_FRAME_INT_ENA_R = crate::BitReader;
67#[doc = "Field `BLC_FRAME_INT_ENA` writer - write 1 to enable blc frame done"]
68pub type BLC_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `LSC_FRAME_INT_ENA` reader - write 1 to enable lsc frame done"]
70pub type LSC_FRAME_INT_ENA_R = crate::BitReader;
71#[doc = "Field `LSC_FRAME_INT_ENA` writer - write 1 to enable lsc frame done"]
72pub type LSC_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `DPC_FRAME_INT_ENA` reader - write 1 to enable dpc frame done"]
74pub type DPC_FRAME_INT_ENA_R = crate::BitReader;
75#[doc = "Field `DPC_FRAME_INT_ENA` writer - write 1 to enable dpc frame done"]
76pub type DPC_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `BF_FRAME_INT_ENA` reader - write 1 to enable bf frame done"]
78pub type BF_FRAME_INT_ENA_R = crate::BitReader;
79#[doc = "Field `BF_FRAME_INT_ENA` writer - write 1 to enable bf frame done"]
80pub type BF_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `DEMOSAIC_FRAME_INT_ENA` reader - write 1 to enable demosaic frame done"]
82pub type DEMOSAIC_FRAME_INT_ENA_R = crate::BitReader;
83#[doc = "Field `DEMOSAIC_FRAME_INT_ENA` writer - write 1 to enable demosaic frame done"]
84pub type DEMOSAIC_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `MEDIAN_FRAME_INT_ENA` reader - write 1 to enable median frame done"]
86pub type MEDIAN_FRAME_INT_ENA_R = crate::BitReader;
87#[doc = "Field `MEDIAN_FRAME_INT_ENA` writer - write 1 to enable median frame done"]
88pub type MEDIAN_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `CCM_FRAME_INT_ENA` reader - write 1 to enable ccm frame done"]
90pub type CCM_FRAME_INT_ENA_R = crate::BitReader;
91#[doc = "Field `CCM_FRAME_INT_ENA` writer - write 1 to enable ccm frame done"]
92pub type CCM_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
93#[doc = "Field `GAMMA_FRAME_INT_ENA` reader - write 1 to enable gamma frame done"]
94pub type GAMMA_FRAME_INT_ENA_R = crate::BitReader;
95#[doc = "Field `GAMMA_FRAME_INT_ENA` writer - write 1 to enable gamma frame done"]
96pub type GAMMA_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
97#[doc = "Field `RGB2YUV_FRAME_INT_ENA` reader - write 1 to enable rgb2yuv frame done"]
98pub type RGB2YUV_FRAME_INT_ENA_R = crate::BitReader;
99#[doc = "Field `RGB2YUV_FRAME_INT_ENA` writer - write 1 to enable rgb2yuv frame done"]
100pub type RGB2YUV_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
101#[doc = "Field `SHARP_FRAME_INT_ENA` reader - write 1 to enable sharp frame done"]
102pub type SHARP_FRAME_INT_ENA_R = crate::BitReader;
103#[doc = "Field `SHARP_FRAME_INT_ENA` writer - write 1 to enable sharp frame done"]
104pub type SHARP_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
105#[doc = "Field `COLOR_FRAME_INT_ENA` reader - write 1 to enable color frame done"]
106pub type COLOR_FRAME_INT_ENA_R = crate::BitReader;
107#[doc = "Field `COLOR_FRAME_INT_ENA` writer - write 1 to enable color frame done"]
108pub type COLOR_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
109#[doc = "Field `YUV2RGB_FRAME_INT_ENA` reader - write 1 to enable yuv2rgb frame done"]
110pub type YUV2RGB_FRAME_INT_ENA_R = crate::BitReader;
111#[doc = "Field `YUV2RGB_FRAME_INT_ENA` writer - write 1 to enable yuv2rgb frame done"]
112pub type YUV2RGB_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
113#[doc = "Field `TAIL_IDI_FRAME_INT_ENA` reader - write 1 to enable isp_tail idi frame_end"]
114pub type TAIL_IDI_FRAME_INT_ENA_R = crate::BitReader;
115#[doc = "Field `TAIL_IDI_FRAME_INT_ENA` writer - write 1 to enable isp_tail idi frame_end"]
116pub type TAIL_IDI_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
117#[doc = "Field `HEADER_IDI_FRAME_INT_ENA` reader - write 1 to enable real input frame end of isp_input"]
118pub type HEADER_IDI_FRAME_INT_ENA_R = crate::BitReader;
119#[doc = "Field `HEADER_IDI_FRAME_INT_ENA` writer - write 1 to enable real input frame end of isp_input"]
120pub type HEADER_IDI_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
121impl R {
122 #[doc = "Bit 0 - write 1 to enable input data type error"]
123 #[inline(always)]
124 pub fn isp_data_type_err_int_ena(&self) -> ISP_DATA_TYPE_ERR_INT_ENA_R {
125 ISP_DATA_TYPE_ERR_INT_ENA_R::new((self.bits & 1) != 0)
126 }
127 #[doc = "Bit 1 - write 1 to enable isp input fifo overflow"]
128 #[inline(always)]
129 pub fn isp_async_fifo_ovf_int_ena(&self) -> ISP_ASYNC_FIFO_OVF_INT_ENA_R {
130 ISP_ASYNC_FIFO_OVF_INT_ENA_R::new(((self.bits >> 1) & 1) != 0)
131 }
132 #[doc = "Bit 2 - write 1 to enable isp input buffer full"]
133 #[inline(always)]
134 pub fn isp_buf_full_int_ena(&self) -> ISP_BUF_FULL_INT_ENA_R {
135 ISP_BUF_FULL_INT_ENA_R::new(((self.bits >> 2) & 1) != 0)
136 }
137 #[doc = "Bit 3 - write 1 to enable hnum and vnum setting format error"]
138 #[inline(always)]
139 pub fn isp_hvnum_setting_err_int_ena(&self) -> ISP_HVNUM_SETTING_ERR_INT_ENA_R {
140 ISP_HVNUM_SETTING_ERR_INT_ENA_R::new(((self.bits >> 3) & 1) != 0)
141 }
142 #[doc = "Bit 4 - write 1 to enable setting invalid reg_data_type"]
143 #[inline(always)]
144 pub fn isp_data_type_setting_err_int_ena(&self) -> ISP_DATA_TYPE_SETTING_ERR_INT_ENA_R {
145 ISP_DATA_TYPE_SETTING_ERR_INT_ENA_R::new(((self.bits >> 4) & 1) != 0)
146 }
147 #[doc = "Bit 5 - write 1 to enable hnum setting unmatch with mipi input"]
148 #[inline(always)]
149 pub fn isp_mipi_hnum_unmatch_int_ena(&self) -> ISP_MIPI_HNUM_UNMATCH_INT_ENA_R {
150 ISP_MIPI_HNUM_UNMATCH_INT_ENA_R::new(((self.bits >> 5) & 1) != 0)
151 }
152 #[doc = "Bit 6 - write 1 to enable dpc check done"]
153 #[inline(always)]
154 pub fn dpc_check_done_int_ena(&self) -> DPC_CHECK_DONE_INT_ENA_R {
155 DPC_CHECK_DONE_INT_ENA_R::new(((self.bits >> 6) & 1) != 0)
156 }
157 #[doc = "Bit 7 - write 1 to enable gamma setting error"]
158 #[inline(always)]
159 pub fn gamma_xcoord_err_int_ena(&self) -> GAMMA_XCOORD_ERR_INT_ENA_R {
160 GAMMA_XCOORD_ERR_INT_ENA_R::new(((self.bits >> 7) & 1) != 0)
161 }
162 #[doc = "Bit 8 - write 1 to enable ae monitor"]
163 #[inline(always)]
164 pub fn ae_monitor_int_ena(&self) -> AE_MONITOR_INT_ENA_R {
165 AE_MONITOR_INT_ENA_R::new(((self.bits >> 8) & 1) != 0)
166 }
167 #[doc = "Bit 9 - write 1 to enable ae"]
168 #[inline(always)]
169 pub fn ae_frame_done_int_ena(&self) -> AE_FRAME_DONE_INT_ENA_R {
170 AE_FRAME_DONE_INT_ENA_R::new(((self.bits >> 9) & 1) != 0)
171 }
172 #[doc = "Bit 10 - write 1 to enable af statistic"]
173 #[inline(always)]
174 pub fn af_fdone_int_ena(&self) -> AF_FDONE_INT_ENA_R {
175 AF_FDONE_INT_ENA_R::new(((self.bits >> 10) & 1) != 0)
176 }
177 #[doc = "Bit 11 - write 1 to enable af monitor"]
178 #[inline(always)]
179 pub fn af_env_int_ena(&self) -> AF_ENV_INT_ENA_R {
180 AF_ENV_INT_ENA_R::new(((self.bits >> 11) & 1) != 0)
181 }
182 #[doc = "Bit 12 - write 1 to enable awb"]
183 #[inline(always)]
184 pub fn awb_fdone_int_ena(&self) -> AWB_FDONE_INT_ENA_R {
185 AWB_FDONE_INT_ENA_R::new(((self.bits >> 12) & 1) != 0)
186 }
187 #[doc = "Bit 13 - write 1 to enable histogram"]
188 #[inline(always)]
189 pub fn hist_fdone_int_ena(&self) -> HIST_FDONE_INT_ENA_R {
190 HIST_FDONE_INT_ENA_R::new(((self.bits >> 13) & 1) != 0)
191 }
192 #[doc = "Bit 14 - write 1 to enable isp frame end"]
193 #[inline(always)]
194 pub fn frame_int_ena(&self) -> FRAME_INT_ENA_R {
195 FRAME_INT_ENA_R::new(((self.bits >> 14) & 1) != 0)
196 }
197 #[doc = "Bit 15 - write 1 to enable blc frame done"]
198 #[inline(always)]
199 pub fn blc_frame_int_ena(&self) -> BLC_FRAME_INT_ENA_R {
200 BLC_FRAME_INT_ENA_R::new(((self.bits >> 15) & 1) != 0)
201 }
202 #[doc = "Bit 16 - write 1 to enable lsc frame done"]
203 #[inline(always)]
204 pub fn lsc_frame_int_ena(&self) -> LSC_FRAME_INT_ENA_R {
205 LSC_FRAME_INT_ENA_R::new(((self.bits >> 16) & 1) != 0)
206 }
207 #[doc = "Bit 17 - write 1 to enable dpc frame done"]
208 #[inline(always)]
209 pub fn dpc_frame_int_ena(&self) -> DPC_FRAME_INT_ENA_R {
210 DPC_FRAME_INT_ENA_R::new(((self.bits >> 17) & 1) != 0)
211 }
212 #[doc = "Bit 18 - write 1 to enable bf frame done"]
213 #[inline(always)]
214 pub fn bf_frame_int_ena(&self) -> BF_FRAME_INT_ENA_R {
215 BF_FRAME_INT_ENA_R::new(((self.bits >> 18) & 1) != 0)
216 }
217 #[doc = "Bit 19 - write 1 to enable demosaic frame done"]
218 #[inline(always)]
219 pub fn demosaic_frame_int_ena(&self) -> DEMOSAIC_FRAME_INT_ENA_R {
220 DEMOSAIC_FRAME_INT_ENA_R::new(((self.bits >> 19) & 1) != 0)
221 }
222 #[doc = "Bit 20 - write 1 to enable median frame done"]
223 #[inline(always)]
224 pub fn median_frame_int_ena(&self) -> MEDIAN_FRAME_INT_ENA_R {
225 MEDIAN_FRAME_INT_ENA_R::new(((self.bits >> 20) & 1) != 0)
226 }
227 #[doc = "Bit 21 - write 1 to enable ccm frame done"]
228 #[inline(always)]
229 pub fn ccm_frame_int_ena(&self) -> CCM_FRAME_INT_ENA_R {
230 CCM_FRAME_INT_ENA_R::new(((self.bits >> 21) & 1) != 0)
231 }
232 #[doc = "Bit 22 - write 1 to enable gamma frame done"]
233 #[inline(always)]
234 pub fn gamma_frame_int_ena(&self) -> GAMMA_FRAME_INT_ENA_R {
235 GAMMA_FRAME_INT_ENA_R::new(((self.bits >> 22) & 1) != 0)
236 }
237 #[doc = "Bit 23 - write 1 to enable rgb2yuv frame done"]
238 #[inline(always)]
239 pub fn rgb2yuv_frame_int_ena(&self) -> RGB2YUV_FRAME_INT_ENA_R {
240 RGB2YUV_FRAME_INT_ENA_R::new(((self.bits >> 23) & 1) != 0)
241 }
242 #[doc = "Bit 24 - write 1 to enable sharp frame done"]
243 #[inline(always)]
244 pub fn sharp_frame_int_ena(&self) -> SHARP_FRAME_INT_ENA_R {
245 SHARP_FRAME_INT_ENA_R::new(((self.bits >> 24) & 1) != 0)
246 }
247 #[doc = "Bit 25 - write 1 to enable color frame done"]
248 #[inline(always)]
249 pub fn color_frame_int_ena(&self) -> COLOR_FRAME_INT_ENA_R {
250 COLOR_FRAME_INT_ENA_R::new(((self.bits >> 25) & 1) != 0)
251 }
252 #[doc = "Bit 26 - write 1 to enable yuv2rgb frame done"]
253 #[inline(always)]
254 pub fn yuv2rgb_frame_int_ena(&self) -> YUV2RGB_FRAME_INT_ENA_R {
255 YUV2RGB_FRAME_INT_ENA_R::new(((self.bits >> 26) & 1) != 0)
256 }
257 #[doc = "Bit 27 - write 1 to enable isp_tail idi frame_end"]
258 #[inline(always)]
259 pub fn tail_idi_frame_int_ena(&self) -> TAIL_IDI_FRAME_INT_ENA_R {
260 TAIL_IDI_FRAME_INT_ENA_R::new(((self.bits >> 27) & 1) != 0)
261 }
262 #[doc = "Bit 28 - write 1 to enable real input frame end of isp_input"]
263 #[inline(always)]
264 pub fn header_idi_frame_int_ena(&self) -> HEADER_IDI_FRAME_INT_ENA_R {
265 HEADER_IDI_FRAME_INT_ENA_R::new(((self.bits >> 28) & 1) != 0)
266 }
267}
268#[cfg(feature = "impl-register-debug")]
269impl core::fmt::Debug for R {
270 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
271 f.debug_struct("INT_ENA")
272 .field(
273 "isp_data_type_err_int_ena",
274 &format_args!("{}", self.isp_data_type_err_int_ena().bit()),
275 )
276 .field(
277 "isp_async_fifo_ovf_int_ena",
278 &format_args!("{}", self.isp_async_fifo_ovf_int_ena().bit()),
279 )
280 .field(
281 "isp_buf_full_int_ena",
282 &format_args!("{}", self.isp_buf_full_int_ena().bit()),
283 )
284 .field(
285 "isp_hvnum_setting_err_int_ena",
286 &format_args!("{}", self.isp_hvnum_setting_err_int_ena().bit()),
287 )
288 .field(
289 "isp_data_type_setting_err_int_ena",
290 &format_args!("{}", self.isp_data_type_setting_err_int_ena().bit()),
291 )
292 .field(
293 "isp_mipi_hnum_unmatch_int_ena",
294 &format_args!("{}", self.isp_mipi_hnum_unmatch_int_ena().bit()),
295 )
296 .field(
297 "dpc_check_done_int_ena",
298 &format_args!("{}", self.dpc_check_done_int_ena().bit()),
299 )
300 .field(
301 "gamma_xcoord_err_int_ena",
302 &format_args!("{}", self.gamma_xcoord_err_int_ena().bit()),
303 )
304 .field(
305 "ae_monitor_int_ena",
306 &format_args!("{}", self.ae_monitor_int_ena().bit()),
307 )
308 .field(
309 "ae_frame_done_int_ena",
310 &format_args!("{}", self.ae_frame_done_int_ena().bit()),
311 )
312 .field(
313 "af_fdone_int_ena",
314 &format_args!("{}", self.af_fdone_int_ena().bit()),
315 )
316 .field(
317 "af_env_int_ena",
318 &format_args!("{}", self.af_env_int_ena().bit()),
319 )
320 .field(
321 "awb_fdone_int_ena",
322 &format_args!("{}", self.awb_fdone_int_ena().bit()),
323 )
324 .field(
325 "hist_fdone_int_ena",
326 &format_args!("{}", self.hist_fdone_int_ena().bit()),
327 )
328 .field(
329 "frame_int_ena",
330 &format_args!("{}", self.frame_int_ena().bit()),
331 )
332 .field(
333 "blc_frame_int_ena",
334 &format_args!("{}", self.blc_frame_int_ena().bit()),
335 )
336 .field(
337 "lsc_frame_int_ena",
338 &format_args!("{}", self.lsc_frame_int_ena().bit()),
339 )
340 .field(
341 "dpc_frame_int_ena",
342 &format_args!("{}", self.dpc_frame_int_ena().bit()),
343 )
344 .field(
345 "bf_frame_int_ena",
346 &format_args!("{}", self.bf_frame_int_ena().bit()),
347 )
348 .field(
349 "demosaic_frame_int_ena",
350 &format_args!("{}", self.demosaic_frame_int_ena().bit()),
351 )
352 .field(
353 "median_frame_int_ena",
354 &format_args!("{}", self.median_frame_int_ena().bit()),
355 )
356 .field(
357 "ccm_frame_int_ena",
358 &format_args!("{}", self.ccm_frame_int_ena().bit()),
359 )
360 .field(
361 "gamma_frame_int_ena",
362 &format_args!("{}", self.gamma_frame_int_ena().bit()),
363 )
364 .field(
365 "rgb2yuv_frame_int_ena",
366 &format_args!("{}", self.rgb2yuv_frame_int_ena().bit()),
367 )
368 .field(
369 "sharp_frame_int_ena",
370 &format_args!("{}", self.sharp_frame_int_ena().bit()),
371 )
372 .field(
373 "color_frame_int_ena",
374 &format_args!("{}", self.color_frame_int_ena().bit()),
375 )
376 .field(
377 "yuv2rgb_frame_int_ena",
378 &format_args!("{}", self.yuv2rgb_frame_int_ena().bit()),
379 )
380 .field(
381 "tail_idi_frame_int_ena",
382 &format_args!("{}", self.tail_idi_frame_int_ena().bit()),
383 )
384 .field(
385 "header_idi_frame_int_ena",
386 &format_args!("{}", self.header_idi_frame_int_ena().bit()),
387 )
388 .finish()
389 }
390}
391#[cfg(feature = "impl-register-debug")]
392impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
393 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
394 core::fmt::Debug::fmt(&self.read(), f)
395 }
396}
397impl W {
398 #[doc = "Bit 0 - write 1 to enable input data type error"]
399 #[inline(always)]
400 #[must_use]
401 pub fn isp_data_type_err_int_ena(&mut self) -> ISP_DATA_TYPE_ERR_INT_ENA_W<INT_ENA_SPEC> {
402 ISP_DATA_TYPE_ERR_INT_ENA_W::new(self, 0)
403 }
404 #[doc = "Bit 1 - write 1 to enable isp input fifo overflow"]
405 #[inline(always)]
406 #[must_use]
407 pub fn isp_async_fifo_ovf_int_ena(&mut self) -> ISP_ASYNC_FIFO_OVF_INT_ENA_W<INT_ENA_SPEC> {
408 ISP_ASYNC_FIFO_OVF_INT_ENA_W::new(self, 1)
409 }
410 #[doc = "Bit 2 - write 1 to enable isp input buffer full"]
411 #[inline(always)]
412 #[must_use]
413 pub fn isp_buf_full_int_ena(&mut self) -> ISP_BUF_FULL_INT_ENA_W<INT_ENA_SPEC> {
414 ISP_BUF_FULL_INT_ENA_W::new(self, 2)
415 }
416 #[doc = "Bit 3 - write 1 to enable hnum and vnum setting format error"]
417 #[inline(always)]
418 #[must_use]
419 pub fn isp_hvnum_setting_err_int_ena(
420 &mut self,
421 ) -> ISP_HVNUM_SETTING_ERR_INT_ENA_W<INT_ENA_SPEC> {
422 ISP_HVNUM_SETTING_ERR_INT_ENA_W::new(self, 3)
423 }
424 #[doc = "Bit 4 - write 1 to enable setting invalid reg_data_type"]
425 #[inline(always)]
426 #[must_use]
427 pub fn isp_data_type_setting_err_int_ena(
428 &mut self,
429 ) -> ISP_DATA_TYPE_SETTING_ERR_INT_ENA_W<INT_ENA_SPEC> {
430 ISP_DATA_TYPE_SETTING_ERR_INT_ENA_W::new(self, 4)
431 }
432 #[doc = "Bit 5 - write 1 to enable hnum setting unmatch with mipi input"]
433 #[inline(always)]
434 #[must_use]
435 pub fn isp_mipi_hnum_unmatch_int_ena(
436 &mut self,
437 ) -> ISP_MIPI_HNUM_UNMATCH_INT_ENA_W<INT_ENA_SPEC> {
438 ISP_MIPI_HNUM_UNMATCH_INT_ENA_W::new(self, 5)
439 }
440 #[doc = "Bit 6 - write 1 to enable dpc check done"]
441 #[inline(always)]
442 #[must_use]
443 pub fn dpc_check_done_int_ena(&mut self) -> DPC_CHECK_DONE_INT_ENA_W<INT_ENA_SPEC> {
444 DPC_CHECK_DONE_INT_ENA_W::new(self, 6)
445 }
446 #[doc = "Bit 7 - write 1 to enable gamma setting error"]
447 #[inline(always)]
448 #[must_use]
449 pub fn gamma_xcoord_err_int_ena(&mut self) -> GAMMA_XCOORD_ERR_INT_ENA_W<INT_ENA_SPEC> {
450 GAMMA_XCOORD_ERR_INT_ENA_W::new(self, 7)
451 }
452 #[doc = "Bit 8 - write 1 to enable ae monitor"]
453 #[inline(always)]
454 #[must_use]
455 pub fn ae_monitor_int_ena(&mut self) -> AE_MONITOR_INT_ENA_W<INT_ENA_SPEC> {
456 AE_MONITOR_INT_ENA_W::new(self, 8)
457 }
458 #[doc = "Bit 9 - write 1 to enable ae"]
459 #[inline(always)]
460 #[must_use]
461 pub fn ae_frame_done_int_ena(&mut self) -> AE_FRAME_DONE_INT_ENA_W<INT_ENA_SPEC> {
462 AE_FRAME_DONE_INT_ENA_W::new(self, 9)
463 }
464 #[doc = "Bit 10 - write 1 to enable af statistic"]
465 #[inline(always)]
466 #[must_use]
467 pub fn af_fdone_int_ena(&mut self) -> AF_FDONE_INT_ENA_W<INT_ENA_SPEC> {
468 AF_FDONE_INT_ENA_W::new(self, 10)
469 }
470 #[doc = "Bit 11 - write 1 to enable af monitor"]
471 #[inline(always)]
472 #[must_use]
473 pub fn af_env_int_ena(&mut self) -> AF_ENV_INT_ENA_W<INT_ENA_SPEC> {
474 AF_ENV_INT_ENA_W::new(self, 11)
475 }
476 #[doc = "Bit 12 - write 1 to enable awb"]
477 #[inline(always)]
478 #[must_use]
479 pub fn awb_fdone_int_ena(&mut self) -> AWB_FDONE_INT_ENA_W<INT_ENA_SPEC> {
480 AWB_FDONE_INT_ENA_W::new(self, 12)
481 }
482 #[doc = "Bit 13 - write 1 to enable histogram"]
483 #[inline(always)]
484 #[must_use]
485 pub fn hist_fdone_int_ena(&mut self) -> HIST_FDONE_INT_ENA_W<INT_ENA_SPEC> {
486 HIST_FDONE_INT_ENA_W::new(self, 13)
487 }
488 #[doc = "Bit 14 - write 1 to enable isp frame end"]
489 #[inline(always)]
490 #[must_use]
491 pub fn frame_int_ena(&mut self) -> FRAME_INT_ENA_W<INT_ENA_SPEC> {
492 FRAME_INT_ENA_W::new(self, 14)
493 }
494 #[doc = "Bit 15 - write 1 to enable blc frame done"]
495 #[inline(always)]
496 #[must_use]
497 pub fn blc_frame_int_ena(&mut self) -> BLC_FRAME_INT_ENA_W<INT_ENA_SPEC> {
498 BLC_FRAME_INT_ENA_W::new(self, 15)
499 }
500 #[doc = "Bit 16 - write 1 to enable lsc frame done"]
501 #[inline(always)]
502 #[must_use]
503 pub fn lsc_frame_int_ena(&mut self) -> LSC_FRAME_INT_ENA_W<INT_ENA_SPEC> {
504 LSC_FRAME_INT_ENA_W::new(self, 16)
505 }
506 #[doc = "Bit 17 - write 1 to enable dpc frame done"]
507 #[inline(always)]
508 #[must_use]
509 pub fn dpc_frame_int_ena(&mut self) -> DPC_FRAME_INT_ENA_W<INT_ENA_SPEC> {
510 DPC_FRAME_INT_ENA_W::new(self, 17)
511 }
512 #[doc = "Bit 18 - write 1 to enable bf frame done"]
513 #[inline(always)]
514 #[must_use]
515 pub fn bf_frame_int_ena(&mut self) -> BF_FRAME_INT_ENA_W<INT_ENA_SPEC> {
516 BF_FRAME_INT_ENA_W::new(self, 18)
517 }
518 #[doc = "Bit 19 - write 1 to enable demosaic frame done"]
519 #[inline(always)]
520 #[must_use]
521 pub fn demosaic_frame_int_ena(&mut self) -> DEMOSAIC_FRAME_INT_ENA_W<INT_ENA_SPEC> {
522 DEMOSAIC_FRAME_INT_ENA_W::new(self, 19)
523 }
524 #[doc = "Bit 20 - write 1 to enable median frame done"]
525 #[inline(always)]
526 #[must_use]
527 pub fn median_frame_int_ena(&mut self) -> MEDIAN_FRAME_INT_ENA_W<INT_ENA_SPEC> {
528 MEDIAN_FRAME_INT_ENA_W::new(self, 20)
529 }
530 #[doc = "Bit 21 - write 1 to enable ccm frame done"]
531 #[inline(always)]
532 #[must_use]
533 pub fn ccm_frame_int_ena(&mut self) -> CCM_FRAME_INT_ENA_W<INT_ENA_SPEC> {
534 CCM_FRAME_INT_ENA_W::new(self, 21)
535 }
536 #[doc = "Bit 22 - write 1 to enable gamma frame done"]
537 #[inline(always)]
538 #[must_use]
539 pub fn gamma_frame_int_ena(&mut self) -> GAMMA_FRAME_INT_ENA_W<INT_ENA_SPEC> {
540 GAMMA_FRAME_INT_ENA_W::new(self, 22)
541 }
542 #[doc = "Bit 23 - write 1 to enable rgb2yuv frame done"]
543 #[inline(always)]
544 #[must_use]
545 pub fn rgb2yuv_frame_int_ena(&mut self) -> RGB2YUV_FRAME_INT_ENA_W<INT_ENA_SPEC> {
546 RGB2YUV_FRAME_INT_ENA_W::new(self, 23)
547 }
548 #[doc = "Bit 24 - write 1 to enable sharp frame done"]
549 #[inline(always)]
550 #[must_use]
551 pub fn sharp_frame_int_ena(&mut self) -> SHARP_FRAME_INT_ENA_W<INT_ENA_SPEC> {
552 SHARP_FRAME_INT_ENA_W::new(self, 24)
553 }
554 #[doc = "Bit 25 - write 1 to enable color frame done"]
555 #[inline(always)]
556 #[must_use]
557 pub fn color_frame_int_ena(&mut self) -> COLOR_FRAME_INT_ENA_W<INT_ENA_SPEC> {
558 COLOR_FRAME_INT_ENA_W::new(self, 25)
559 }
560 #[doc = "Bit 26 - write 1 to enable yuv2rgb frame done"]
561 #[inline(always)]
562 #[must_use]
563 pub fn yuv2rgb_frame_int_ena(&mut self) -> YUV2RGB_FRAME_INT_ENA_W<INT_ENA_SPEC> {
564 YUV2RGB_FRAME_INT_ENA_W::new(self, 26)
565 }
566 #[doc = "Bit 27 - write 1 to enable isp_tail idi frame_end"]
567 #[inline(always)]
568 #[must_use]
569 pub fn tail_idi_frame_int_ena(&mut self) -> TAIL_IDI_FRAME_INT_ENA_W<INT_ENA_SPEC> {
570 TAIL_IDI_FRAME_INT_ENA_W::new(self, 27)
571 }
572 #[doc = "Bit 28 - write 1 to enable real input frame end of isp_input"]
573 #[inline(always)]
574 #[must_use]
575 pub fn header_idi_frame_int_ena(&mut self) -> HEADER_IDI_FRAME_INT_ENA_W<INT_ENA_SPEC> {
576 HEADER_IDI_FRAME_INT_ENA_W::new(self, 28)
577 }
578}
579#[doc = "interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
580pub struct INT_ENA_SPEC;
581impl crate::RegisterSpec for INT_ENA_SPEC {
582 type Ux = u32;
583}
584#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
585impl crate::Readable for INT_ENA_SPEC {}
586#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
587impl crate::Writable for INT_ENA_SPEC {
588 type Safety = crate::Unsafe;
589 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
590 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
591}
592#[doc = "`reset()` method sets INT_ENA to value 0xc3"]
593impl crate::Resettable for INT_ENA_SPEC {
594 const RESET_VALUE: u32 = 0xc3;
595}