esp32p4/isp/
dma_cntl.rs

1#[doc = "Register `DMA_CNTL` reader"]
2pub type R = crate::R<DMA_CNTL_SPEC>;
3#[doc = "Register `DMA_CNTL` writer"]
4pub type W = crate::W<DMA_CNTL_SPEC>;
5#[doc = "Field `DMA_EN` writer - write 1 to triger dma to get 1 frame"]
6pub type DMA_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `DMA_UPDATE` reader - write 1 to update reg_dma_burst_len &amp; reg_dma_data_type"]
8pub type DMA_UPDATE_R = crate::BitReader;
9#[doc = "Field `DMA_UPDATE` writer - write 1 to update reg_dma_burst_len &amp; reg_dma_data_type"]
10pub type DMA_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `DMA_DATA_TYPE` reader - this field configures the idi data type for image data"]
12pub type DMA_DATA_TYPE_R = crate::FieldReader;
13#[doc = "Field `DMA_DATA_TYPE` writer - this field configures the idi data type for image data"]
14pub type DMA_DATA_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
15#[doc = "Field `DMA_BURST_LEN` reader - this field configures dma burst len when data source is dma. set according to dma_msize, it is the number of 64bits in a dma transfer"]
16pub type DMA_BURST_LEN_R = crate::FieldReader<u16>;
17#[doc = "Field `DMA_BURST_LEN` writer - this field configures dma burst len when data source is dma. set according to dma_msize, it is the number of 64bits in a dma transfer"]
18pub type DMA_BURST_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
19#[doc = "Field `DMA_INTERVAL` reader - this field configures dma req interval, 12'b1: 1 cycle, 12'b11 2 cycle ..."]
20pub type DMA_INTERVAL_R = crate::FieldReader<u16>;
21#[doc = "Field `DMA_INTERVAL` writer - this field configures dma req interval, 12'b1: 1 cycle, 12'b11 2 cycle ..."]
22pub type DMA_INTERVAL_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
23impl R {
24    #[doc = "Bit 1 - write 1 to update reg_dma_burst_len &amp; reg_dma_data_type"]
25    #[inline(always)]
26    pub fn dma_update(&self) -> DMA_UPDATE_R {
27        DMA_UPDATE_R::new(((self.bits >> 1) & 1) != 0)
28    }
29    #[doc = "Bits 2:7 - this field configures the idi data type for image data"]
30    #[inline(always)]
31    pub fn dma_data_type(&self) -> DMA_DATA_TYPE_R {
32        DMA_DATA_TYPE_R::new(((self.bits >> 2) & 0x3f) as u8)
33    }
34    #[doc = "Bits 8:19 - this field configures dma burst len when data source is dma. set according to dma_msize, it is the number of 64bits in a dma transfer"]
35    #[inline(always)]
36    pub fn dma_burst_len(&self) -> DMA_BURST_LEN_R {
37        DMA_BURST_LEN_R::new(((self.bits >> 8) & 0x0fff) as u16)
38    }
39    #[doc = "Bits 20:31 - this field configures dma req interval, 12'b1: 1 cycle, 12'b11 2 cycle ..."]
40    #[inline(always)]
41    pub fn dma_interval(&self) -> DMA_INTERVAL_R {
42        DMA_INTERVAL_R::new(((self.bits >> 20) & 0x0fff) as u16)
43    }
44}
45#[cfg(feature = "impl-register-debug")]
46impl core::fmt::Debug for R {
47    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
48        f.debug_struct("DMA_CNTL")
49            .field("dma_update", &format_args!("{}", self.dma_update().bit()))
50            .field(
51                "dma_data_type",
52                &format_args!("{}", self.dma_data_type().bits()),
53            )
54            .field(
55                "dma_burst_len",
56                &format_args!("{}", self.dma_burst_len().bits()),
57            )
58            .field(
59                "dma_interval",
60                &format_args!("{}", self.dma_interval().bits()),
61            )
62            .finish()
63    }
64}
65#[cfg(feature = "impl-register-debug")]
66impl core::fmt::Debug for crate::generic::Reg<DMA_CNTL_SPEC> {
67    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
68        core::fmt::Debug::fmt(&self.read(), f)
69    }
70}
71impl W {
72    #[doc = "Bit 0 - write 1 to triger dma to get 1 frame"]
73    #[inline(always)]
74    #[must_use]
75    pub fn dma_en(&mut self) -> DMA_EN_W<DMA_CNTL_SPEC> {
76        DMA_EN_W::new(self, 0)
77    }
78    #[doc = "Bit 1 - write 1 to update reg_dma_burst_len &amp; reg_dma_data_type"]
79    #[inline(always)]
80    #[must_use]
81    pub fn dma_update(&mut self) -> DMA_UPDATE_W<DMA_CNTL_SPEC> {
82        DMA_UPDATE_W::new(self, 1)
83    }
84    #[doc = "Bits 2:7 - this field configures the idi data type for image data"]
85    #[inline(always)]
86    #[must_use]
87    pub fn dma_data_type(&mut self) -> DMA_DATA_TYPE_W<DMA_CNTL_SPEC> {
88        DMA_DATA_TYPE_W::new(self, 2)
89    }
90    #[doc = "Bits 8:19 - this field configures dma burst len when data source is dma. set according to dma_msize, it is the number of 64bits in a dma transfer"]
91    #[inline(always)]
92    #[must_use]
93    pub fn dma_burst_len(&mut self) -> DMA_BURST_LEN_W<DMA_CNTL_SPEC> {
94        DMA_BURST_LEN_W::new(self, 8)
95    }
96    #[doc = "Bits 20:31 - this field configures dma req interval, 12'b1: 1 cycle, 12'b11 2 cycle ..."]
97    #[inline(always)]
98    #[must_use]
99    pub fn dma_interval(&mut self) -> DMA_INTERVAL_W<DMA_CNTL_SPEC> {
100        DMA_INTERVAL_W::new(self, 20)
101    }
102}
103#[doc = "isp dma source trans control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_cntl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
104pub struct DMA_CNTL_SPEC;
105impl crate::RegisterSpec for DMA_CNTL_SPEC {
106    type Ux = u32;
107}
108#[doc = "`read()` method returns [`dma_cntl::R`](R) reader structure"]
109impl crate::Readable for DMA_CNTL_SPEC {}
110#[doc = "`write(|w| ..)` method takes [`dma_cntl::W`](W) writer structure"]
111impl crate::Writable for DMA_CNTL_SPEC {
112    type Safety = crate::Unsafe;
113    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
114    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
115}
116#[doc = "`reset()` method sets DMA_CNTL to value 0x0010_80a8"]
117impl crate::Resettable for DMA_CNTL_SPEC {
118    const RESET_VALUE: u32 = 0x0010_80a8;
119}
esp32p4/isp/dma_cntl.rs

esp32p4/isp/
dma_cntl.rs
