esp32p4/hp_sys/
core_dbus_timeout.rs

1#[doc = "Register `CORE_DBUS_TIMEOUT` reader"]
2pub type R = crate::R<CORE_DBUS_TIMEOUT_SPEC>;
3#[doc = "Register `CORE_DBUS_TIMEOUT` writer"]
4pub type W = crate::W<CORE_DBUS_TIMEOUT_SPEC>;
5#[doc = "Field `EN` reader - set this field to 1 to enable hp core0&amp;1 dbus timeout handle"]
6pub type EN_R = crate::BitReader;
7#[doc = "Field `EN` writer - set this field to 1 to enable hp core0&amp;1 dbus timeout handle"]
8pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `THRES` reader - This field used to set hp core0&amp;1 dbus timeout threshold"]
10pub type THRES_R = crate::FieldReader<u16>;
11#[doc = "Field `THRES` writer - This field used to set hp core0&amp;1 dbus timeout threshold"]
12pub type THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13impl R {
14    #[doc = "Bit 0 - set this field to 1 to enable hp core0&amp;1 dbus timeout handle"]
15    #[inline(always)]
16    pub fn en(&self) -> EN_R {
17        EN_R::new((self.bits & 1) != 0)
18    }
19    #[doc = "Bits 1:16 - This field used to set hp core0&amp;1 dbus timeout threshold"]
20    #[inline(always)]
21    pub fn thres(&self) -> THRES_R {
22        THRES_R::new(((self.bits >> 1) & 0xffff) as u16)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("CORE_DBUS_TIMEOUT")
29            .field("en", &format_args!("{}", self.en().bit()))
30            .field("thres", &format_args!("{}", self.thres().bits()))
31            .finish()
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for crate::generic::Reg<CORE_DBUS_TIMEOUT_SPEC> {
36    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
37        core::fmt::Debug::fmt(&self.read(), f)
38    }
39}
40impl W {
41    #[doc = "Bit 0 - set this field to 1 to enable hp core0&amp;1 dbus timeout handle"]
42    #[inline(always)]
43    #[must_use]
44    pub fn en(&mut self) -> EN_W<CORE_DBUS_TIMEOUT_SPEC> {
45        EN_W::new(self, 0)
46    }
47    #[doc = "Bits 1:16 - This field used to set hp core0&amp;1 dbus timeout threshold"]
48    #[inline(always)]
49    #[must_use]
50    pub fn thres(&mut self) -> THRES_W<CORE_DBUS_TIMEOUT_SPEC> {
51        THRES_W::new(self, 1)
52    }
53}
54#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_dbus_timeout::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_dbus_timeout::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
55pub struct CORE_DBUS_TIMEOUT_SPEC;
56impl crate::RegisterSpec for CORE_DBUS_TIMEOUT_SPEC {
57    type Ux = u32;
58}
59#[doc = "`read()` method returns [`core_dbus_timeout::R`](R) reader structure"]
60impl crate::Readable for CORE_DBUS_TIMEOUT_SPEC {}
61#[doc = "`write(|w| ..)` method takes [`core_dbus_timeout::W`](W) writer structure"]
62impl crate::Writable for CORE_DBUS_TIMEOUT_SPEC {
63    type Safety = crate::Unsafe;
64    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
65    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
66}
67#[doc = "`reset()` method sets CORE_DBUS_TIMEOUT to value 0x0001_ffff"]
68impl crate::Resettable for CORE_DBUS_TIMEOUT_SPEC {
69    const RESET_VALUE: u32 = 0x0001_ffff;
70}
esp32p4/hp_sys/core_dbus_timeout.rs

esp32p4/hp_sys/
core_dbus_timeout.rs
