esp32p4/hp_sys/
cache_clk_config.rs

1#[doc = "Register `CACHE_CLK_CONFIG` reader"]
2pub type R = crate::R<CACHE_CLK_CONFIG_SPEC>;
3#[doc = "Register `CACHE_CLK_CONFIG` writer"]
4pub type W = crate::W<CACHE_CLK_CONFIG_SPEC>;
5#[doc = "Field `REG_L2_CACHE_CLK_ON` reader - l2 cahce clk enable"]
6pub type REG_L2_CACHE_CLK_ON_R = crate::BitReader;
7#[doc = "Field `REG_L2_CACHE_CLK_ON` writer - l2 cahce clk enable"]
8pub type REG_L2_CACHE_CLK_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `REG_L1_D_CACHE_CLK_ON` reader - l1 dcahce clk enable"]
10pub type REG_L1_D_CACHE_CLK_ON_R = crate::BitReader;
11#[doc = "Field `REG_L1_D_CACHE_CLK_ON` writer - l1 dcahce clk enable"]
12pub type REG_L1_D_CACHE_CLK_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `REG_L1_I1_CACHE_CLK_ON` reader - l1 icahce1 clk enable"]
14pub type REG_L1_I1_CACHE_CLK_ON_R = crate::BitReader;
15#[doc = "Field `REG_L1_I1_CACHE_CLK_ON` writer - l1 icahce1 clk enable"]
16pub type REG_L1_I1_CACHE_CLK_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `REG_L1_I0_CACHE_CLK_ON` reader - l1 icahce0 clk enable"]
18pub type REG_L1_I0_CACHE_CLK_ON_R = crate::BitReader;
19#[doc = "Field `REG_L1_I0_CACHE_CLK_ON` writer - l1 icahce0 clk enable"]
20pub type REG_L1_I0_CACHE_CLK_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 0 - l2 cahce clk enable"]
23    #[inline(always)]
24    pub fn reg_l2_cache_clk_on(&self) -> REG_L2_CACHE_CLK_ON_R {
25        REG_L2_CACHE_CLK_ON_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - l1 dcahce clk enable"]
28    #[inline(always)]
29    pub fn reg_l1_d_cache_clk_on(&self) -> REG_L1_D_CACHE_CLK_ON_R {
30        REG_L1_D_CACHE_CLK_ON_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 4 - l1 icahce1 clk enable"]
33    #[inline(always)]
34    pub fn reg_l1_i1_cache_clk_on(&self) -> REG_L1_I1_CACHE_CLK_ON_R {
35        REG_L1_I1_CACHE_CLK_ON_R::new(((self.bits >> 4) & 1) != 0)
36    }
37    #[doc = "Bit 5 - l1 icahce0 clk enable"]
38    #[inline(always)]
39    pub fn reg_l1_i0_cache_clk_on(&self) -> REG_L1_I0_CACHE_CLK_ON_R {
40        REG_L1_I0_CACHE_CLK_ON_R::new(((self.bits >> 5) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("CACHE_CLK_CONFIG")
47            .field(
48                "reg_l2_cache_clk_on",
49                &format_args!("{}", self.reg_l2_cache_clk_on().bit()),
50            )
51            .field(
52                "reg_l1_d_cache_clk_on",
53                &format_args!("{}", self.reg_l1_d_cache_clk_on().bit()),
54            )
55            .field(
56                "reg_l1_i1_cache_clk_on",
57                &format_args!("{}", self.reg_l1_i1_cache_clk_on().bit()),
58            )
59            .field(
60                "reg_l1_i0_cache_clk_on",
61                &format_args!("{}", self.reg_l1_i0_cache_clk_on().bit()),
62            )
63            .finish()
64    }
65}
66#[cfg(feature = "impl-register-debug")]
67impl core::fmt::Debug for crate::generic::Reg<CACHE_CLK_CONFIG_SPEC> {
68    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
69        core::fmt::Debug::fmt(&self.read(), f)
70    }
71}
72impl W {
73    #[doc = "Bit 0 - l2 cahce clk enable"]
74    #[inline(always)]
75    #[must_use]
76    pub fn reg_l2_cache_clk_on(&mut self) -> REG_L2_CACHE_CLK_ON_W<CACHE_CLK_CONFIG_SPEC> {
77        REG_L2_CACHE_CLK_ON_W::new(self, 0)
78    }
79    #[doc = "Bit 1 - l1 dcahce clk enable"]
80    #[inline(always)]
81    #[must_use]
82    pub fn reg_l1_d_cache_clk_on(&mut self) -> REG_L1_D_CACHE_CLK_ON_W<CACHE_CLK_CONFIG_SPEC> {
83        REG_L1_D_CACHE_CLK_ON_W::new(self, 1)
84    }
85    #[doc = "Bit 4 - l1 icahce1 clk enable"]
86    #[inline(always)]
87    #[must_use]
88    pub fn reg_l1_i1_cache_clk_on(&mut self) -> REG_L1_I1_CACHE_CLK_ON_W<CACHE_CLK_CONFIG_SPEC> {
89        REG_L1_I1_CACHE_CLK_ON_W::new(self, 4)
90    }
91    #[doc = "Bit 5 - l1 icahce0 clk enable"]
92    #[inline(always)]
93    #[must_use]
94    pub fn reg_l1_i0_cache_clk_on(&mut self) -> REG_L1_I0_CACHE_CLK_ON_W<CACHE_CLK_CONFIG_SPEC> {
95        REG_L1_I0_CACHE_CLK_ON_W::new(self, 5)
96    }
97}
98#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_clk_config::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cache_clk_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
99pub struct CACHE_CLK_CONFIG_SPEC;
100impl crate::RegisterSpec for CACHE_CLK_CONFIG_SPEC {
101    type Ux = u32;
102}
103#[doc = "`read()` method returns [`cache_clk_config::R`](R) reader structure"]
104impl crate::Readable for CACHE_CLK_CONFIG_SPEC {}
105#[doc = "`write(|w| ..)` method takes [`cache_clk_config::W`](W) writer structure"]
106impl crate::Writable for CACHE_CLK_CONFIG_SPEC {
107    type Safety = crate::Unsafe;
108    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
109    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
110}
111#[doc = "`reset()` method sets CACHE_CLK_CONFIG to value 0x33"]
112impl crate::Resettable for CACHE_CLK_CONFIG_SPEC {
113    const RESET_VALUE: u32 = 0x33;
114}
esp32p4/hp_sys/cache_clk_config.rs

esp32p4/hp_sys/
cache_clk_config.rs
