esp32p4/cache/
l1_dcache_autoload_sct3_addr.rs

1#[doc = "Register `L1_DCACHE_AUTOLOAD_SCT3_ADDR` reader"]
2pub type R = crate::R<L1_DCACHE_AUTOLOAD_SCT3_ADDR_SPEC>;
3#[doc = "Register `L1_DCACHE_AUTOLOAD_SCT3_ADDR` writer"]
4pub type W = crate::W<L1_DCACHE_AUTOLOAD_SCT3_ADDR_SPEC>;
5#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT3_ADDR` reader - Those bits are used to configure the start virtual address of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_SIZE and L1_DCACHE_AUTOLOAD_SCT3_ENA."]
6pub type L1_DCACHE_AUTOLOAD_SCT3_ADDR_R = crate::FieldReader<u32>;
7#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT3_ADDR` writer - Those bits are used to configure the start virtual address of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_SIZE and L1_DCACHE_AUTOLOAD_SCT3_ENA."]
8pub type L1_DCACHE_AUTOLOAD_SCT3_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
9impl R {
10    #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_SIZE and L1_DCACHE_AUTOLOAD_SCT3_ENA."]
11    #[inline(always)]
12    pub fn l1_dcache_autoload_sct3_addr(&self) -> L1_DCACHE_AUTOLOAD_SCT3_ADDR_R {
13        L1_DCACHE_AUTOLOAD_SCT3_ADDR_R::new(self.bits)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("L1_DCACHE_AUTOLOAD_SCT3_ADDR")
20            .field(
21                "l1_dcache_autoload_sct3_addr",
22                &format_args!("{}", self.l1_dcache_autoload_sct3_addr().bits()),
23            )
24            .finish()
25    }
26}
27#[cfg(feature = "impl-register-debug")]
28impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_AUTOLOAD_SCT3_ADDR_SPEC> {
29    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
30        core::fmt::Debug::fmt(&self.read(), f)
31    }
32}
33impl W {
34    #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_SIZE and L1_DCACHE_AUTOLOAD_SCT3_ENA."]
35    #[inline(always)]
36    #[must_use]
37    pub fn l1_dcache_autoload_sct3_addr(
38        &mut self,
39    ) -> L1_DCACHE_AUTOLOAD_SCT3_ADDR_W<L1_DCACHE_AUTOLOAD_SCT3_ADDR_SPEC> {
40        L1_DCACHE_AUTOLOAD_SCT3_ADDR_W::new(self, 0)
41    }
42}
43#[doc = "L1 data Cache autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct3_addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct3_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
44pub struct L1_DCACHE_AUTOLOAD_SCT3_ADDR_SPEC;
45impl crate::RegisterSpec for L1_DCACHE_AUTOLOAD_SCT3_ADDR_SPEC {
46    type Ux = u32;
47}
48#[doc = "`read()` method returns [`l1_dcache_autoload_sct3_addr::R`](R) reader structure"]
49impl crate::Readable for L1_DCACHE_AUTOLOAD_SCT3_ADDR_SPEC {}
50#[doc = "`write(|w| ..)` method takes [`l1_dcache_autoload_sct3_addr::W`](W) writer structure"]
51impl crate::Writable for L1_DCACHE_AUTOLOAD_SCT3_ADDR_SPEC {
52    type Safety = crate::Unsafe;
53    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
54    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
55}
56#[doc = "`reset()` method sets L1_DCACHE_AUTOLOAD_SCT3_ADDR to value 0"]
57impl crate::Resettable for L1_DCACHE_AUTOLOAD_SCT3_ADDR_SPEC {
58    const RESET_VALUE: u32 = 0;
59}
esp32p4/cache/l1_dcache_autoload_sct3_addr.rs

esp32p4/cache/
l1_dcache_autoload_sct3_addr.rs
