esp32p4/cache/
l1_cache_acs_fail_int_clr.rs

1#[doc = "Register `L1_CACHE_ACS_FAIL_INT_CLR` reader"]
2pub type R = crate::R<L1_CACHE_ACS_FAIL_INT_CLR_SPEC>;
3#[doc = "Register `L1_CACHE_ACS_FAIL_INT_CLR` writer"]
4pub type W = crate::W<L1_CACHE_ACS_FAIL_INT_CLR_SPEC>;
5#[doc = "Field `L1_ICACHE0_FAIL_INT_CLR` writer - The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0."]
6pub type L1_ICACHE0_FAIL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `L1_ICACHE1_FAIL_INT_CLR` writer - The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1."]
8pub type L1_ICACHE1_FAIL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `L1_ICACHE2_FAIL_INT_CLR` reader - Reserved"]
10pub type L1_ICACHE2_FAIL_INT_CLR_R = crate::BitReader;
11#[doc = "Field `L1_ICACHE3_FAIL_INT_CLR` reader - Reserved"]
12pub type L1_ICACHE3_FAIL_INT_CLR_R = crate::BitReader;
13#[doc = "Field `L1_DCACHE_FAIL_INT_CLR` writer - The bit is used to clear interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache."]
14pub type L1_DCACHE_FAIL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
15impl R {
16    #[doc = "Bit 2 - Reserved"]
17    #[inline(always)]
18    pub fn l1_icache2_fail_int_clr(&self) -> L1_ICACHE2_FAIL_INT_CLR_R {
19        L1_ICACHE2_FAIL_INT_CLR_R::new(((self.bits >> 2) & 1) != 0)
20    }
21    #[doc = "Bit 3 - Reserved"]
22    #[inline(always)]
23    pub fn l1_icache3_fail_int_clr(&self) -> L1_ICACHE3_FAIL_INT_CLR_R {
24        L1_ICACHE3_FAIL_INT_CLR_R::new(((self.bits >> 3) & 1) != 0)
25    }
26}
27#[cfg(feature = "impl-register-debug")]
28impl core::fmt::Debug for R {
29    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
30        f.debug_struct("L1_CACHE_ACS_FAIL_INT_CLR")
31            .field(
32                "l1_icache2_fail_int_clr",
33                &format_args!("{}", self.l1_icache2_fail_int_clr().bit()),
34            )
35            .field(
36                "l1_icache3_fail_int_clr",
37                &format_args!("{}", self.l1_icache3_fail_int_clr().bit()),
38            )
39            .finish()
40    }
41}
42#[cfg(feature = "impl-register-debug")]
43impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ACS_FAIL_INT_CLR_SPEC> {
44    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
45        core::fmt::Debug::fmt(&self.read(), f)
46    }
47}
48impl W {
49    #[doc = "Bit 0 - The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0."]
50    #[inline(always)]
51    #[must_use]
52    pub fn l1_icache0_fail_int_clr(
53        &mut self,
54    ) -> L1_ICACHE0_FAIL_INT_CLR_W<L1_CACHE_ACS_FAIL_INT_CLR_SPEC> {
55        L1_ICACHE0_FAIL_INT_CLR_W::new(self, 0)
56    }
57    #[doc = "Bit 1 - The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1."]
58    #[inline(always)]
59    #[must_use]
60    pub fn l1_icache1_fail_int_clr(
61        &mut self,
62    ) -> L1_ICACHE1_FAIL_INT_CLR_W<L1_CACHE_ACS_FAIL_INT_CLR_SPEC> {
63        L1_ICACHE1_FAIL_INT_CLR_W::new(self, 1)
64    }
65    #[doc = "Bit 4 - The bit is used to clear interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache."]
66    #[inline(always)]
67    #[must_use]
68    pub fn l1_dcache_fail_int_clr(
69        &mut self,
70    ) -> L1_DCACHE_FAIL_INT_CLR_W<L1_CACHE_ACS_FAIL_INT_CLR_SPEC> {
71        L1_DCACHE_FAIL_INT_CLR_W::new(self, 4)
72    }
73}
74#[doc = "L1-Cache Access Fail Interrupt clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_fail_int_clr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_fail_int_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
75pub struct L1_CACHE_ACS_FAIL_INT_CLR_SPEC;
76impl crate::RegisterSpec for L1_CACHE_ACS_FAIL_INT_CLR_SPEC {
77    type Ux = u32;
78}
79#[doc = "`read()` method returns [`l1_cache_acs_fail_int_clr::R`](R) reader structure"]
80impl crate::Readable for L1_CACHE_ACS_FAIL_INT_CLR_SPEC {}
81#[doc = "`write(|w| ..)` method takes [`l1_cache_acs_fail_int_clr::W`](W) writer structure"]
82impl crate::Writable for L1_CACHE_ACS_FAIL_INT_CLR_SPEC {
83    type Safety = crate::Unsafe;
84    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
85    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
86}
87#[doc = "`reset()` method sets L1_CACHE_ACS_FAIL_INT_CLR to value 0"]
88impl crate::Resettable for L1_CACHE_ACS_FAIL_INT_CLR_SPEC {
89    const RESET_VALUE: u32 = 0;
90}
esp32p4/cache/l1_cache_acs_fail_int_clr.rs

esp32p4/cache/
l1_cache_acs_fail_int_clr.rs
