esp32p4/spi1/
cache_fctrl.rs

1#[doc = "Register `CACHE_FCTRL` reader"]
2pub type R = crate::R<CACHE_FCTRL_SPEC>;
3#[doc = "Register `CACHE_FCTRL` writer"]
4pub type W = crate::W<CACHE_FCTRL_SPEC>;
5#[doc = "Field `CACHE_USR_ADDR_4BYTE` reader - For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable."]
6pub type CACHE_USR_ADDR_4BYTE_R = crate::BitReader;
7#[doc = "Field `CACHE_USR_ADDR_4BYTE` writer - For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable."]
8pub type CACHE_USR_ADDR_4BYTE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `FDIN_DUAL` reader - For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
10pub type FDIN_DUAL_R = crate::BitReader;
11#[doc = "Field `FDIN_DUAL` writer - For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
12pub type FDIN_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FDOUT_DUAL` reader - For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
14pub type FDOUT_DUAL_R = crate::BitReader;
15#[doc = "Field `FDOUT_DUAL` writer - For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
16pub type FDOUT_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FADDR_DUAL` reader - For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
18pub type FADDR_DUAL_R = crate::BitReader;
19#[doc = "Field `FADDR_DUAL` writer - For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
20pub type FADDR_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `FDIN_QUAD` reader - For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
22pub type FDIN_QUAD_R = crate::BitReader;
23#[doc = "Field `FDIN_QUAD` writer - For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
24pub type FDIN_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `FDOUT_QUAD` reader - For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
26pub type FDOUT_QUAD_R = crate::BitReader;
27#[doc = "Field `FDOUT_QUAD` writer - For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
28pub type FDOUT_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `FADDR_QUAD` reader - For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
30pub type FADDR_QUAD_R = crate::BitReader;
31#[doc = "Field `FADDR_QUAD` writer - For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
32pub type FADDR_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34    #[doc = "Bit 1 - For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable."]
35    #[inline(always)]
36    pub fn cache_usr_addr_4byte(&self) -> CACHE_USR_ADDR_4BYTE_R {
37        CACHE_USR_ADDR_4BYTE_R::new(((self.bits >> 1) & 1) != 0)
38    }
39    #[doc = "Bit 3 - For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
40    #[inline(always)]
41    pub fn fdin_dual(&self) -> FDIN_DUAL_R {
42        FDIN_DUAL_R::new(((self.bits >> 3) & 1) != 0)
43    }
44    #[doc = "Bit 4 - For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
45    #[inline(always)]
46    pub fn fdout_dual(&self) -> FDOUT_DUAL_R {
47        FDOUT_DUAL_R::new(((self.bits >> 4) & 1) != 0)
48    }
49    #[doc = "Bit 5 - For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
50    #[inline(always)]
51    pub fn faddr_dual(&self) -> FADDR_DUAL_R {
52        FADDR_DUAL_R::new(((self.bits >> 5) & 1) != 0)
53    }
54    #[doc = "Bit 6 - For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
55    #[inline(always)]
56    pub fn fdin_quad(&self) -> FDIN_QUAD_R {
57        FDIN_QUAD_R::new(((self.bits >> 6) & 1) != 0)
58    }
59    #[doc = "Bit 7 - For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
60    #[inline(always)]
61    pub fn fdout_quad(&self) -> FDOUT_QUAD_R {
62        FDOUT_QUAD_R::new(((self.bits >> 7) & 1) != 0)
63    }
64    #[doc = "Bit 8 - For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
65    #[inline(always)]
66    pub fn faddr_quad(&self) -> FADDR_QUAD_R {
67        FADDR_QUAD_R::new(((self.bits >> 8) & 1) != 0)
68    }
69}
70#[cfg(feature = "impl-register-debug")]
71impl core::fmt::Debug for R {
72    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
73        f.debug_struct("CACHE_FCTRL")
74            .field(
75                "cache_usr_addr_4byte",
76                &format_args!("{}", self.cache_usr_addr_4byte().bit()),
77            )
78            .field("fdin_dual", &format_args!("{}", self.fdin_dual().bit()))
79            .field("fdout_dual", &format_args!("{}", self.fdout_dual().bit()))
80            .field("faddr_dual", &format_args!("{}", self.faddr_dual().bit()))
81            .field("fdin_quad", &format_args!("{}", self.fdin_quad().bit()))
82            .field("fdout_quad", &format_args!("{}", self.fdout_quad().bit()))
83            .field("faddr_quad", &format_args!("{}", self.faddr_quad().bit()))
84            .finish()
85    }
86}
87#[cfg(feature = "impl-register-debug")]
88impl core::fmt::Debug for crate::generic::Reg<CACHE_FCTRL_SPEC> {
89    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
90        core::fmt::Debug::fmt(&self.read(), f)
91    }
92}
93impl W {
94    #[doc = "Bit 1 - For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable."]
95    #[inline(always)]
96    #[must_use]
97    pub fn cache_usr_addr_4byte(&mut self) -> CACHE_USR_ADDR_4BYTE_W<CACHE_FCTRL_SPEC> {
98        CACHE_USR_ADDR_4BYTE_W::new(self, 1)
99    }
100    #[doc = "Bit 3 - For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
101    #[inline(always)]
102    #[must_use]
103    pub fn fdin_dual(&mut self) -> FDIN_DUAL_W<CACHE_FCTRL_SPEC> {
104        FDIN_DUAL_W::new(self, 3)
105    }
106    #[doc = "Bit 4 - For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
107    #[inline(always)]
108    #[must_use]
109    pub fn fdout_dual(&mut self) -> FDOUT_DUAL_W<CACHE_FCTRL_SPEC> {
110        FDOUT_DUAL_W::new(self, 4)
111    }
112    #[doc = "Bit 5 - For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
113    #[inline(always)]
114    #[must_use]
115    pub fn faddr_dual(&mut self) -> FADDR_DUAL_W<CACHE_FCTRL_SPEC> {
116        FADDR_DUAL_W::new(self, 5)
117    }
118    #[doc = "Bit 6 - For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
119    #[inline(always)]
120    #[must_use]
121    pub fn fdin_quad(&mut self) -> FDIN_QUAD_W<CACHE_FCTRL_SPEC> {
122        FDIN_QUAD_W::new(self, 6)
123    }
124    #[doc = "Bit 7 - For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
125    #[inline(always)]
126    #[must_use]
127    pub fn fdout_quad(&mut self) -> FDOUT_QUAD_W<CACHE_FCTRL_SPEC> {
128        FDOUT_QUAD_W::new(self, 7)
129    }
130    #[doc = "Bit 8 - For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
131    #[inline(always)]
132    #[must_use]
133    pub fn faddr_quad(&mut self) -> FADDR_QUAD_W<CACHE_FCTRL_SPEC> {
134        FADDR_QUAD_W::new(self, 8)
135    }
136}
137#[doc = "SPI1 bit mode control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_fctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cache_fctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
138pub struct CACHE_FCTRL_SPEC;
139impl crate::RegisterSpec for CACHE_FCTRL_SPEC {
140    type Ux = u32;
141}
142#[doc = "`read()` method returns [`cache_fctrl::R`](R) reader structure"]
143impl crate::Readable for CACHE_FCTRL_SPEC {}
144#[doc = "`write(|w| ..)` method takes [`cache_fctrl::W`](W) writer structure"]
145impl crate::Writable for CACHE_FCTRL_SPEC {
146    type Safety = crate::Unsafe;
147    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
148    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
149}
150#[doc = "`reset()` method sets CACHE_FCTRL to value 0"]
151impl crate::Resettable for CACHE_FCTRL_SPEC {
152    const RESET_VALUE: u32 = 0;
153}
esp32p4/spi1/cache_fctrl.rs

esp32p4/spi1/
cache_fctrl.rs
