1#[doc = "Register `INT_RAW` reader"]
2pub type R = crate::R<INT_RAW_SPEC>;
3#[doc = "Register `INT_RAW` writer"]
4pub type W = crate::W<INT_RAW_SPEC>;
5#[doc = "Field `SLV_ST_END` reader - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others"]
6pub type SLV_ST_END_R = crate::BitReader;
7#[doc = "Field `SLV_ST_END` writer - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others"]
8pub type SLV_ST_END_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `MST_ST_END` reader - The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others."]
10pub type MST_ST_END_R = crate::BitReader;
11#[doc = "Field `MST_ST_END` writer - The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others."]
12pub type MST_ST_END_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `ECC_ERR` reader - The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered."]
14pub type ECC_ERR_R = crate::BitReader;
15#[doc = "Field `ECC_ERR` writer - The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered."]
16pub type ECC_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `PMS_REJECT` reader - The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others."]
18pub type PMS_REJECT_R = crate::BitReader;
19#[doc = "Field `PMS_REJECT` writer - The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others."]
20pub type PMS_REJECT_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `AXI_RADDR_ERR` reader - The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others."]
22pub type AXI_RADDR_ERR_R = crate::BitReader;
23#[doc = "Field `AXI_RADDR_ERR` writer - The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others."]
24pub type AXI_RADDR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `AXI_WR_FLASH_ERR` reader - The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others."]
26pub type AXI_WR_FLASH_ERR_R = crate::BitReader;
27#[doc = "Field `AXI_WR_FLASH_ERR` writer - The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others."]
28pub type AXI_WR_FLASH_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `AXI_WADDR_ERR` reader - The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others."]
30pub type AXI_WADDR_ERR_R = crate::BitReader;
31#[doc = "Field `AXI_WADDR_ERR` writer - The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others."]
32pub type AXI_WADDR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `DQS0_AFIFO_OVF` reader - The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS1 is overflow."]
34pub type DQS0_AFIFO_OVF_R = crate::BitReader;
35#[doc = "Field `DQS0_AFIFO_OVF` writer - The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS1 is overflow."]
36pub type DQS0_AFIFO_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `DQS1_AFIFO_OVF` reader - The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS is overflow."]
38pub type DQS1_AFIFO_OVF_R = crate::BitReader;
39#[doc = "Field `DQS1_AFIFO_OVF` writer - The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS is overflow."]
40pub type DQS1_AFIFO_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `BUS_FIFO1_UDF` reader - The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is underflow."]
42pub type BUS_FIFO1_UDF_R = crate::BitReader;
43#[doc = "Field `BUS_FIFO1_UDF` writer - The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is underflow."]
44pub type BUS_FIFO1_UDF_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `BUS_FIFO0_UDF` reader - The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is underflow."]
46pub type BUS_FIFO0_UDF_R = crate::BitReader;
47#[doc = "Field `BUS_FIFO0_UDF` writer - The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is underflow."]
48pub type BUS_FIFO0_UDF_W<'a, REG> = crate::BitWriter<'a, REG>;
49impl R {
50 #[doc = "Bit 3 - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others"]
51 #[inline(always)]
52 pub fn slv_st_end(&self) -> SLV_ST_END_R {
53 SLV_ST_END_R::new(((self.bits >> 3) & 1) != 0)
54 }
55 #[doc = "Bit 4 - The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others."]
56 #[inline(always)]
57 pub fn mst_st_end(&self) -> MST_ST_END_R {
58 MST_ST_END_R::new(((self.bits >> 4) & 1) != 0)
59 }
60 #[doc = "Bit 5 - The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered."]
61 #[inline(always)]
62 pub fn ecc_err(&self) -> ECC_ERR_R {
63 ECC_ERR_R::new(((self.bits >> 5) & 1) != 0)
64 }
65 #[doc = "Bit 6 - The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others."]
66 #[inline(always)]
67 pub fn pms_reject(&self) -> PMS_REJECT_R {
68 PMS_REJECT_R::new(((self.bits >> 6) & 1) != 0)
69 }
70 #[doc = "Bit 7 - The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others."]
71 #[inline(always)]
72 pub fn axi_raddr_err(&self) -> AXI_RADDR_ERR_R {
73 AXI_RADDR_ERR_R::new(((self.bits >> 7) & 1) != 0)
74 }
75 #[doc = "Bit 8 - The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others."]
76 #[inline(always)]
77 pub fn axi_wr_flash_err(&self) -> AXI_WR_FLASH_ERR_R {
78 AXI_WR_FLASH_ERR_R::new(((self.bits >> 8) & 1) != 0)
79 }
80 #[doc = "Bit 9 - The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others."]
81 #[inline(always)]
82 pub fn axi_waddr_err(&self) -> AXI_WADDR_ERR_R {
83 AXI_WADDR_ERR_R::new(((self.bits >> 9) & 1) != 0)
84 }
85 #[doc = "Bit 28 - The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS1 is overflow."]
86 #[inline(always)]
87 pub fn dqs0_afifo_ovf(&self) -> DQS0_AFIFO_OVF_R {
88 DQS0_AFIFO_OVF_R::new(((self.bits >> 28) & 1) != 0)
89 }
90 #[doc = "Bit 29 - The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS is overflow."]
91 #[inline(always)]
92 pub fn dqs1_afifo_ovf(&self) -> DQS1_AFIFO_OVF_R {
93 DQS1_AFIFO_OVF_R::new(((self.bits >> 29) & 1) != 0)
94 }
95 #[doc = "Bit 30 - The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is underflow."]
96 #[inline(always)]
97 pub fn bus_fifo1_udf(&self) -> BUS_FIFO1_UDF_R {
98 BUS_FIFO1_UDF_R::new(((self.bits >> 30) & 1) != 0)
99 }
100 #[doc = "Bit 31 - The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is underflow."]
101 #[inline(always)]
102 pub fn bus_fifo0_udf(&self) -> BUS_FIFO0_UDF_R {
103 BUS_FIFO0_UDF_R::new(((self.bits >> 31) & 1) != 0)
104 }
105}
106#[cfg(feature = "impl-register-debug")]
107impl core::fmt::Debug for R {
108 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
109 f.debug_struct("INT_RAW")
110 .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
111 .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
112 .field("ecc_err", &format_args!("{}", self.ecc_err().bit()))
113 .field("pms_reject", &format_args!("{}", self.pms_reject().bit()))
114 .field(
115 "axi_raddr_err",
116 &format_args!("{}", self.axi_raddr_err().bit()),
117 )
118 .field(
119 "axi_wr_flash_err",
120 &format_args!("{}", self.axi_wr_flash_err().bit()),
121 )
122 .field(
123 "axi_waddr_err",
124 &format_args!("{}", self.axi_waddr_err().bit()),
125 )
126 .field(
127 "dqs0_afifo_ovf",
128 &format_args!("{}", self.dqs0_afifo_ovf().bit()),
129 )
130 .field(
131 "dqs1_afifo_ovf",
132 &format_args!("{}", self.dqs1_afifo_ovf().bit()),
133 )
134 .field(
135 "bus_fifo1_udf",
136 &format_args!("{}", self.bus_fifo1_udf().bit()),
137 )
138 .field(
139 "bus_fifo0_udf",
140 &format_args!("{}", self.bus_fifo0_udf().bit()),
141 )
142 .finish()
143 }
144}
145#[cfg(feature = "impl-register-debug")]
146impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
147 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
148 core::fmt::Debug::fmt(&self.read(), f)
149 }
150}
151impl W {
152 #[doc = "Bit 3 - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others"]
153 #[inline(always)]
154 #[must_use]
155 pub fn slv_st_end(&mut self) -> SLV_ST_END_W<INT_RAW_SPEC> {
156 SLV_ST_END_W::new(self, 3)
157 }
158 #[doc = "Bit 4 - The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others."]
159 #[inline(always)]
160 #[must_use]
161 pub fn mst_st_end(&mut self) -> MST_ST_END_W<INT_RAW_SPEC> {
162 MST_ST_END_W::new(self, 4)
163 }
164 #[doc = "Bit 5 - The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered."]
165 #[inline(always)]
166 #[must_use]
167 pub fn ecc_err(&mut self) -> ECC_ERR_W<INT_RAW_SPEC> {
168 ECC_ERR_W::new(self, 5)
169 }
170 #[doc = "Bit 6 - The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others."]
171 #[inline(always)]
172 #[must_use]
173 pub fn pms_reject(&mut self) -> PMS_REJECT_W<INT_RAW_SPEC> {
174 PMS_REJECT_W::new(self, 6)
175 }
176 #[doc = "Bit 7 - The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others."]
177 #[inline(always)]
178 #[must_use]
179 pub fn axi_raddr_err(&mut self) -> AXI_RADDR_ERR_W<INT_RAW_SPEC> {
180 AXI_RADDR_ERR_W::new(self, 7)
181 }
182 #[doc = "Bit 8 - The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others."]
183 #[inline(always)]
184 #[must_use]
185 pub fn axi_wr_flash_err(&mut self) -> AXI_WR_FLASH_ERR_W<INT_RAW_SPEC> {
186 AXI_WR_FLASH_ERR_W::new(self, 8)
187 }
188 #[doc = "Bit 9 - The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others."]
189 #[inline(always)]
190 #[must_use]
191 pub fn axi_waddr_err(&mut self) -> AXI_WADDR_ERR_W<INT_RAW_SPEC> {
192 AXI_WADDR_ERR_W::new(self, 9)
193 }
194 #[doc = "Bit 28 - The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS1 is overflow."]
195 #[inline(always)]
196 #[must_use]
197 pub fn dqs0_afifo_ovf(&mut self) -> DQS0_AFIFO_OVF_W<INT_RAW_SPEC> {
198 DQS0_AFIFO_OVF_W::new(self, 28)
199 }
200 #[doc = "Bit 29 - The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS is overflow."]
201 #[inline(always)]
202 #[must_use]
203 pub fn dqs1_afifo_ovf(&mut self) -> DQS1_AFIFO_OVF_W<INT_RAW_SPEC> {
204 DQS1_AFIFO_OVF_W::new(self, 29)
205 }
206 #[doc = "Bit 30 - The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is underflow."]
207 #[inline(always)]
208 #[must_use]
209 pub fn bus_fifo1_udf(&mut self) -> BUS_FIFO1_UDF_W<INT_RAW_SPEC> {
210 BUS_FIFO1_UDF_W::new(self, 30)
211 }
212 #[doc = "Bit 31 - The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is underflow."]
213 #[inline(always)]
214 #[must_use]
215 pub fn bus_fifo0_udf(&mut self) -> BUS_FIFO0_UDF_W<INT_RAW_SPEC> {
216 BUS_FIFO0_UDF_W::new(self, 31)
217 }
218}
219#[doc = "SPI0 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
220pub struct INT_RAW_SPEC;
221impl crate::RegisterSpec for INT_RAW_SPEC {
222 type Ux = u32;
223}
224#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
225impl crate::Readable for INT_RAW_SPEC {}
226#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"]
227impl crate::Writable for INT_RAW_SPEC {
228 type Safety = crate::Unsafe;
229 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
230 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
231}
232#[doc = "`reset()` method sets INT_RAW to value 0"]
233impl crate::Resettable for INT_RAW_SPEC {
234 const RESET_VALUE: u32 = 0;
235}