Module usb_device

Full-speed USB Serial/JTAG Controller

Modules

bus_reset_st

USB Bus reset status register

chip_rst

CDC-ACM chip reset control.

conf0

PHY hardware configuration.

config_update

Configuration registers’ value update

date

Date register

eco_cell_ctrl_48

Reserved.

eco_cell_ctrl_apb

Reserved.

eco_high_48

Reserved.

eco_high_apb

Reserved.

eco_low_48

Reserved.

eco_low_apb

Reserved.

ep1

FIFO access for the CDC-ACM data IN and OUT endpoints.

ep1_conf

Configuration and control registers for the CDC-ACM FIFOs.

fram_num

Last received SOF frame index register.

get_line_code_w0

W0 of GET_LINE_CODING command.

get_line_code_w1

W1 of GET_LINE_CODING command.

in_ep0_st

Control IN endpoint status information.

in_ep1_st

CDC-ACM IN endpoint status information.

in_ep2_st

CDC-ACM interrupt IN endpoint status information.

in_ep3_st

JTAG IN endpoint status information.

int_clr

Interrupt clear status register.

int_ena

Interrupt enable status register.

int_raw

Interrupt raw status register.

int_st

Interrupt status register.

jfifo_st

JTAG FIFO status and control registers.

mem_conf

Memory power control

misc_conf

Clock enable control

out_ep0_st

Control OUT endpoint status information.

out_ep1_st

CDC-ACM OUT endpoint status information.

out_ep2_st

JTAG OUT endpoint status information.

ser_afifo_config

Serial AFIFO configure register

set_line_code_w0

W0 of SET_LINE_CODING command.

set_line_code_w1

W1 of SET_LINE_CODING command.

sram_ctrl

PPA SRAM Control Register

test

Registers used for debugging the PHY.

Structs

RegisterBlock

Register block

Type Aliases

BUS_RESET_ST

BUS_RESET_ST (r) register accessor: USB Bus reset status register

CHIP_RST

CHIP_RST (rw) register accessor: CDC-ACM chip reset control.

CONF0

CONF0 (rw) register accessor: PHY hardware configuration.

CONFIG_UPDATE

CONFIG_UPDATE (w) register accessor: Configuration registers’ value update

DATE

DATE (rw) register accessor: Date register

ECO_CELL_CTRL_48

ECO_CELL_CTRL_48 (rw) register accessor: Reserved.

ECO_CELL_CTRL_APB

ECO_CELL_CTRL_APB (rw) register accessor: Reserved.

ECO_HIGH_48

ECO_HIGH_48 (rw) register accessor: Reserved.

ECO_HIGH_APB

ECO_HIGH_APB (rw) register accessor: Reserved.

ECO_LOW_48

ECO_LOW_48 (rw) register accessor: Reserved.

ECO_LOW_APB

ECO_LOW_APB (rw) register accessor: Reserved.

EP1

EP1 (rw) register accessor: FIFO access for the CDC-ACM data IN and OUT endpoints.

EP1_CONF

EP1_CONF (rw) register accessor: Configuration and control registers for the CDC-ACM FIFOs.

FRAM_NUM

FRAM_NUM (r) register accessor: Last received SOF frame index register.

GET_LINE_CODE_W0

GET_LINE_CODE_W0 (rw) register accessor: W0 of GET_LINE_CODING command.

GET_LINE_CODE_W1

GET_LINE_CODE_W1 (rw) register accessor: W1 of GET_LINE_CODING command.

INT_CLR

INT_CLR (w) register accessor: Interrupt clear status register.

INT_ENA

INT_ENA (rw) register accessor: Interrupt enable status register.

INT_RAW

INT_RAW (rw) register accessor: Interrupt raw status register.

INT_ST

INT_ST (r) register accessor: Interrupt status register.

IN_EP0_ST

IN_EP0_ST (r) register accessor: Control IN endpoint status information.

IN_EP1_ST

IN_EP1_ST (r) register accessor: CDC-ACM IN endpoint status information.

IN_EP2_ST

IN_EP2_ST (r) register accessor: CDC-ACM interrupt IN endpoint status information.

IN_EP3_ST

IN_EP3_ST (r) register accessor: JTAG IN endpoint status information.

JFIFO_ST

JFIFO_ST (rw) register accessor: JTAG FIFO status and control registers.

MEM_CONF

MEM_CONF (rw) register accessor: Memory power control

MISC_CONF

MISC_CONF (rw) register accessor: Clock enable control

OUT_EP0_ST

OUT_EP0_ST (r) register accessor: Control OUT endpoint status information.

OUT_EP1_ST

OUT_EP1_ST (r) register accessor: CDC-ACM OUT endpoint status information.

OUT_EP2_ST

OUT_EP2_ST (r) register accessor: JTAG OUT endpoint status information.

SER_AFIFO_CONFIG

SER_AFIFO_CONFIG (rw) register accessor: Serial AFIFO configure register

SET_LINE_CODE_W0

SET_LINE_CODE_W0 (r) register accessor: W0 of SET_LINE_CODING command.

SET_LINE_CODE_W1

SET_LINE_CODE_W1 (r) register accessor: W1 of SET_LINE_CODING command.

SRAM_CTRL

SRAM_CTRL (rw) register accessor: PPA SRAM Control Register

TEST

TEST (rw) register accessor: Registers used for debugging the PHY.