Expand description
CACHE Peripheral
Modulesยง
- clock_
gate - Clock gate control register
- date
- Version control register
- l1_
bypass_ cache_ conf - Bypass Cache configure register
- l1_
cache_ acs_ cnt_ ctrl - Cache Access Counter enable and clear register
- l1_
cache_ acs_ cnt_ int_ clr - Cache Access Counter Interrupt clear register
- l1_
cache_ acs_ cnt_ int_ ena - Cache Access Counter Interrupt enable register
- l1_
cache_ acs_ cnt_ int_ raw - Cache Access Counter Interrupt raw register
- l1_
cache_ acs_ cnt_ int_ st - Cache Access Counter Interrupt status register
- l1_
cache_ acs_ fail_ ctrl - Cache Access Fail Configuration register
- l1_
cache_ acs_ fail_ int_ clr - L1-Cache Access Fail Interrupt clear register
- l1_
cache_ acs_ fail_ int_ ena - Cache Access Fail Interrupt enable register
- l1_
cache_ acs_ fail_ int_ raw - Cache Access Fail Interrupt raw register
- l1_
cache_ acs_ fail_ int_ st - Cache Access Fail Interrupt status register
- l1_
cache_ atomic_ conf - L1 Cache atomic feature configure register
- l1_
cache_ autoload_ buf_ clr_ ctrl - Cache Autoload buffer clear control register
- l1_
cache_ data_ mem_ acs_ conf - Cache data memory access configure register
- l1_
cache_ data_ mem_ power_ ctrl - Cache data memory power control register
- l1_
cache_ debug_ bus - Cache Tag/data memory content register
- l1_
cache_ freeze_ ctrl - Cache Freeze control register
- l1_
cache_ object_ ctrl - Cache Tag and Data memory Object control register
- l1_
cache_ preload_ rst_ ctrl - Cache Preload Reset control register
- l1_
cache_ sync_ rst_ ctrl - Cache Sync Reset control register
- l1_
cache_ tag_ mem_ acs_ conf - Cache tag memory access configure register
- l1_
cache_ tag_ mem_ power_ ctrl - Cache tag memory power control register
- l1_
cache_ vaddr - Cache Vaddr register
- l1_
cache_ way_ object - Cache Tag and Data memory way register
- l1_
cache_ wrap_ around_ ctrl - Cache wrap around control register
- l1_
dbus0_ acs_ conflict_ cnt - L1-DCache bus0 Conflict-Access Counter register
- l1_
dbus0_ acs_ hit_ cnt - L1-DCache bus0 Hit-Access Counter register
- l1_
dbus0_ acs_ miss_ cnt - L1-DCache bus0 Miss-Access Counter register
- l1_
dbus0_ acs_ nxtlvl_ rd_ cnt - L1-DCache bus0 Next-Level-Access Counter register
- l1_
dbus0_ acs_ nxtlvl_ wr_ cnt - L1-DCache bus0 WB-Access Counter register
- l1_
dbus1_ acs_ conflict_ cnt - L1-DCache bus1 Conflict-Access Counter register
- l1_
dbus1_ acs_ hit_ cnt - L1-DCache bus1 Hit-Access Counter register
- l1_
dbus1_ acs_ miss_ cnt - L1-DCache bus1 Miss-Access Counter register
- l1_
dbus1_ acs_ nxtlvl_ rd_ cnt - L1-DCache bus1 Next-Level-Access Counter register
- l1_
dbus1_ acs_ nxtlvl_ wr_ cnt - L1-DCache bus1 WB-Access Counter register
- l1_
dbus2_ acs_ conflict_ cnt - L1-DCache bus2 Conflict-Access Counter register
- l1_
dbus2_ acs_ hit_ cnt - L1-DCache bus2 Hit-Access Counter register
- l1_
dbus2_ acs_ miss_ cnt - L1-DCache bus2 Miss-Access Counter register
- l1_
dbus2_ acs_ nxtlvl_ rd_ cnt - L1-DCache bus2 Next-Level-Access Counter register
- l1_
dbus2_ acs_ nxtlvl_ wr_ cnt - L1-DCache bus2 WB-Access Counter register
- l1_
dbus3_ acs_ conflict_ cnt - L1-DCache bus3 Conflict-Access Counter register
- l1_
dbus3_ acs_ hit_ cnt - L1-DCache bus3 Hit-Access Counter register
- l1_
dbus3_ acs_ miss_ cnt - L1-DCache bus3 Miss-Access Counter register
- l1_
dbus3_ acs_ nxtlvl_ rd_ cnt - L1-DCache bus3 Next-Level-Access Counter register
- l1_
dbus3_ acs_ nxtlvl_ wr_ cnt - L1-DCache bus3 WB-Access Counter register
- l1_
dcache_ acs_ fail_ addr - L1-DCache Access Fail Address information register
- l1_
dcache_ acs_ fail_ id_ attr - L1-DCache Access Fail ID/attribution information register
- l1_
dcache_ autoload_ ctrl - L1 data Cache autoload-operation control register
- l1_
dcache_ autoload_ sct0_ addr - L1 data Cache autoload section 0 address configure register
- l1_
dcache_ autoload_ sct0_ size - L1 data Cache autoload section 0 size configure register
- l1_
dcache_ autoload_ sct1_ addr - L1 data Cache autoload section 1 address configure register
- l1_
dcache_ autoload_ sct1_ size - L1 data Cache autoload section 1 size configure register
- l1_
dcache_ autoload_ sct2_ addr - L1 data Cache autoload section 2 address configure register
- l1_
dcache_ autoload_ sct2_ size - L1 data Cache autoload section 2 size configure register
- l1_
dcache_ autoload_ sct3_ addr - L1 data Cache autoload section 1 address configure register
- l1_
dcache_ autoload_ sct3_ size - L1 data Cache autoload section 1 size configure register
- l1_
dcache_ blocksize_ conf - L1 data Cache BlockSize mode configure register
- l1_
dcache_ cachesize_ conf - L1 data Cache CacheSize mode configure register
- l1_
dcache_ ctrl - L1 data Cache(L1-DCache) control register
- l1_
dcache_ preload_ addr - L1 data Cache preload address configure register
- l1_
dcache_ preload_ ctrl - L1 data Cache preload-operation control register
- l1_
dcache_ preload_ size - L1 data Cache preload size configure register
- l1_
dcache_ prelock_ conf - L1 data Cache prelock configure register
- l1_
dcache_ prelock_ sct0_ addr - L1 data Cache prelock section0 address configure register
- l1_
dcache_ prelock_ sct1_ addr - L1 data Cache prelock section1 address configure register
- l1_
dcache_ prelock_ sct_ size - L1 data Cache prelock section size configure register
- l1_
ibus0_ acs_ conflict_ cnt - L1-ICache bus0 Conflict-Access Counter register
- l1_
ibus0_ acs_ hit_ cnt - L1-ICache bus0 Hit-Access Counter register
- l1_
ibus0_ acs_ miss_ cnt - L1-ICache bus0 Miss-Access Counter register
- l1_
ibus0_ acs_ nxtlvl_ rd_ cnt - L1-ICache bus0 Next-Level-Access Counter register
- l1_
ibus1_ acs_ conflict_ cnt - L1-ICache bus1 Conflict-Access Counter register
- l1_
ibus1_ acs_ hit_ cnt - L1-ICache bus1 Hit-Access Counter register
- l1_
ibus1_ acs_ miss_ cnt - L1-ICache bus1 Miss-Access Counter register
- l1_
ibus1_ acs_ nxtlvl_ rd_ cnt - L1-ICache bus1 Next-Level-Access Counter register
- l1_
ibus2_ acs_ conflict_ cnt - L1-ICache bus2 Conflict-Access Counter register
- l1_
ibus2_ acs_ hit_ cnt - L1-ICache bus2 Hit-Access Counter register
- l1_
ibus2_ acs_ miss_ cnt - L1-ICache bus2 Miss-Access Counter register
- l1_
ibus2_ acs_ nxtlvl_ rd_ cnt - L1-ICache bus2 Next-Level-Access Counter register
- l1_
ibus3_ acs_ conflict_ cnt - L1-ICache bus3 Conflict-Access Counter register
- l1_
ibus3_ acs_ hit_ cnt - L1-ICache bus3 Hit-Access Counter register
- l1_
ibus3_ acs_ miss_ cnt - L1-ICache bus3 Miss-Access Counter register
- l1_
ibus3_ acs_ nxtlvl_ rd_ cnt - L1-ICache bus3 Next-Level-Access Counter register
- l1_
icache0_ acs_ fail_ addr - L1-ICache0 Access Fail Address information register
- l1_
icache0_ acs_ fail_ id_ attr - L1-ICache0 Access Fail ID/attribution information register
- l1_
icache0_ autoload_ ctrl - L1 instruction Cache 0 autoload-operation control register
- l1_
icache0_ autoload_ sct0_ addr - L1 instruction Cache 0 autoload section 0 address configure register
- l1_
icache0_ autoload_ sct0_ size - L1 instruction Cache 0 autoload section 0 size configure register
- l1_
icache0_ autoload_ sct1_ addr - L1 instruction Cache 0 autoload section 1 address configure register
- l1_
icache0_ autoload_ sct1_ size - L1 instruction Cache 0 autoload section 1 size configure register
- l1_
icache0_ preload_ addr - L1 instruction Cache 0 preload address configure register
- l1_
icache0_ preload_ ctrl - L1 instruction Cache 0 preload-operation control register
- l1_
icache0_ preload_ size - L1 instruction Cache 0 preload size configure register
- l1_
icache0_ prelock_ conf - L1 instruction Cache 0 prelock configure register
- l1_
icache0_ prelock_ sct0_ addr - L1 instruction Cache 0 prelock section0 address configure register
- l1_
icache0_ prelock_ sct1_ addr - L1 instruction Cache 0 prelock section1 address configure register
- l1_
icache0_ prelock_ sct_ size - L1 instruction Cache 0 prelock section size configure register
- l1_
icache1_ acs_ fail_ addr - L1-ICache0 Access Fail Address information register
- l1_
icache1_ acs_ fail_ id_ attr - L1-ICache0 Access Fail ID/attribution information register
- l1_
icache1_ autoload_ ctrl - L1 instruction Cache 1 autoload-operation control register
- l1_
icache1_ autoload_ sct0_ addr - L1 instruction Cache 1 autoload section 0 address configure register
- l1_
icache1_ autoload_ sct0_ size - L1 instruction Cache 1 autoload section 0 size configure register
- l1_
icache1_ autoload_ sct1_ addr - L1 instruction Cache 1 autoload section 1 address configure register
- l1_
icache1_ autoload_ sct1_ size - L1 instruction Cache 1 autoload section 1 size configure register
- l1_
icache1_ preload_ addr - L1 instruction Cache 1 preload address configure register
- l1_
icache1_ preload_ ctrl - L1 instruction Cache 1 preload-operation control register
- l1_
icache1_ preload_ size - L1 instruction Cache 1 preload size configure register
- l1_
icache1_ prelock_ conf - L1 instruction Cache 1 prelock configure register
- l1_
icache1_ prelock_ sct0_ addr - L1 instruction Cache 1 prelock section0 address configure register
- l1_
icache1_ prelock_ sct1_ addr - L1 instruction Cache 1 prelock section1 address configure register
- l1_
icache1_ prelock_ sct_ size - L1 instruction Cache 1 prelock section size configure register
- l1_
icache2_ acs_ fail_ addr - L1-ICache0 Access Fail Address information register
- l1_
icache2_ acs_ fail_ id_ attr - L1-ICache0 Access Fail ID/attribution information register
- l1_
icache2_ autoload_ ctrl - L1 instruction Cache 2 autoload-operation control register
- l1_
icache2_ autoload_ sct0_ addr - L1 instruction Cache 2 autoload section 0 address configure register
- l1_
icache2_ autoload_ sct0_ size - L1 instruction Cache 2 autoload section 0 size configure register
- l1_
icache2_ autoload_ sct1_ addr - L1 instruction Cache 2 autoload section 1 address configure register
- l1_
icache2_ autoload_ sct1_ size - L1 instruction Cache 2 autoload section 1 size configure register
- l1_
icache2_ preload_ addr - L1 instruction Cache 2 preload address configure register
- l1_
icache2_ preload_ ctrl - L1 instruction Cache 2 preload-operation control register
- l1_
icache2_ preload_ size - L1 instruction Cache 2 preload size configure register
- l1_
icache2_ prelock_ conf - L1 instruction Cache 2 prelock configure register
- l1_
icache2_ prelock_ sct0_ addr - L1 instruction Cache 2 prelock section0 address configure register
- l1_
icache2_ prelock_ sct1_ addr - L1 instruction Cache 2 prelock section1 address configure register
- l1_
icache2_ prelock_ sct_ size - L1 instruction Cache 2 prelock section size configure register
- l1_
icache3_ acs_ fail_ addr - L1-ICache0 Access Fail Address information register
- l1_
icache3_ acs_ fail_ id_ attr - L1-ICache0 Access Fail ID/attribution information register
- l1_
icache3_ autoload_ ctrl - L1 instruction Cache 3 autoload-operation control register
- l1_
icache3_ autoload_ sct0_ addr - L1 instruction Cache 3 autoload section 0 address configure register
- l1_
icache3_ autoload_ sct0_ size - L1 instruction Cache 3 autoload section 0 size configure register
- l1_
icache3_ autoload_ sct1_ addr - L1 instruction Cache 3 autoload section 1 address configure register
- l1_
icache3_ autoload_ sct1_ size - L1 instruction Cache 3 autoload section 1 size configure register
- l1_
icache3_ preload_ addr - L1 instruction Cache 3 preload address configure register
- l1_
icache3_ preload_ ctrl - L1 instruction Cache 3 preload-operation control register
- l1_
icache3_ preload_ size - L1 instruction Cache 3 preload size configure register
- l1_
icache3_ prelock_ conf - L1 instruction Cache 3 prelock configure register
- l1_
icache3_ prelock_ sct0_ addr - L1 instruction Cache 3 prelock section0 address configure register
- l1_
icache3_ prelock_ sct1_ addr - L1 instruction Cache 3 prelock section1 address configure register
- l1_
icache3_ prelock_ sct_ size - L1 instruction Cache 3 prelock section size configure register
- l1_
icache_ blocksize_ conf - L1 instruction Cache BlockSize mode configure register
- l1_
icache_ cachesize_ conf - L1 instruction Cache CacheSize mode configure register
- l1_
icache_ ctrl - L1 instruction Cache(L1-ICache) control register
- l1_
unallocate_ buffer_ clear - Unallocate request buffer clear registers
- l2_
bypass_ cache_ conf - Bypass Cache configure register
- l2_
cache_ access_ attr_ ctrl - L2 cache access attribute control register
- l2_
cache_ acs_ cnt_ ctrl - Cache Access Counter enable and clear register
- l2_
cache_ acs_ cnt_ int_ clr - Cache Access Counter Interrupt clear register
- l2_
cache_ acs_ cnt_ int_ ena - Cache Access Counter Interrupt enable register
- l2_
cache_ acs_ cnt_ int_ raw - Cache Access Counter Interrupt raw register
- l2_
cache_ acs_ cnt_ int_ st - Cache Access Counter Interrupt status register
- l2_
cache_ acs_ fail_ addr - L2-Cache Access Fail Address information register
- l2_
cache_ acs_ fail_ ctrl - Cache Access Fail Configuration register
- l2_
cache_ acs_ fail_ id_ attr - L2-Cache Access Fail ID/attribution information register
- l2_
cache_ acs_ fail_ int_ clr - L1-Cache Access Fail Interrupt clear register
- l2_
cache_ acs_ fail_ int_ ena - Cache Access Fail Interrupt enable register
- l2_
cache_ acs_ fail_ int_ raw - Cache Access Fail Interrupt raw register
- l2_
cache_ acs_ fail_ int_ st - Cache Access Fail Interrupt status register
- l2_
cache_ autoload_ buf_ clr_ ctrl - Cache Autoload buffer clear control register
- l2_
cache_ autoload_ ctrl - L2 Cache autoload-operation control register
- l2_
cache_ autoload_ sct0_ addr - L2 Cache autoload section 0 address configure register
- l2_
cache_ autoload_ sct0_ size - L2 Cache autoload section 0 size configure register
- l2_
cache_ autoload_ sct1_ addr - L2 Cache autoload section 1 address configure register
- l2_
cache_ autoload_ sct1_ size - L2 Cache autoload section 1 size configure register
- l2_
cache_ autoload_ sct2_ addr - L2 Cache autoload section 2 address configure register
- l2_
cache_ autoload_ sct2_ size - L2 Cache autoload section 2 size configure register
- l2_
cache_ autoload_ sct3_ addr - L2 Cache autoload section 3 address configure register
- l2_
cache_ autoload_ sct3_ size - L2 Cache autoload section 3 size configure register
- l2_
cache_ blocksize_ conf - L2 Cache BlockSize mode configure register
- l2_
cache_ cachesize_ conf - L2 Cache CacheSize mode configure register
- l2_
cache_ ctrl - L2 Cache(L2-Cache) control register
- l2_
cache_ data_ mem_ acs_ conf - Cache data memory access configure register
- l2_
cache_ data_ mem_ power_ ctrl - Cache data memory power control register
- l2_
cache_ debug_ bus - Cache Tag/data memory content register
- l2_
cache_ freeze_ ctrl - Cache Freeze control register
- l2_
cache_ object_ ctrl - Cache Tag and Data memory Object control register
- l2_
cache_ preload_ addr - L2 Cache preload address configure register
- l2_
cache_ preload_ ctrl - L2 Cache preload-operation control register
- l2_
cache_ preload_ rst_ ctrl - Cache Preload Reset control register
- l2_
cache_ preload_ size - L2 Cache preload size configure register
- l2_
cache_ prelock_ conf - L2 Cache prelock configure register
- l2_
cache_ prelock_ sct0_ addr - L2 Cache prelock section0 address configure register
- l2_
cache_ prelock_ sct1_ addr - L2 Cache prelock section1 address configure register
- l2_
cache_ prelock_ sct_ size - L2 Cache prelock section size configure register
- l2_
cache_ sync_ preload_ exception - Cache Sync/Preload Operation exception register
- l2_
cache_ sync_ preload_ int_ clr - Sync Preload operation Interrupt clear register
- l2_
cache_ sync_ preload_ int_ ena - L1-Cache Access Fail Interrupt enable register
- l2_
cache_ sync_ preload_ int_ raw - Sync Preload operation Interrupt raw register
- l2_
cache_ sync_ preload_ int_ st - L1-Cache Access Fail Interrupt status register
- l2_
cache_ sync_ rst_ ctrl - Cache Sync Reset control register
- l2_
cache_ tag_ mem_ acs_ conf - Cache tag memory access configure register
- l2_
cache_ tag_ mem_ power_ ctrl - Cache tag memory power control register
- l2_
cache_ vaddr - Cache Vaddr register
- l2_
cache_ way_ object - Cache Tag and Data memory way register
- l2_
cache_ wrap_ around_ ctrl - Cache wrap around control register
- l2_
dbus0_ acs_ conflict_ cnt - L2-Cache bus0 Conflict-Access Counter register
- l2_
dbus0_ acs_ hit_ cnt - L2-Cache bus0 Hit-Access Counter register
- l2_
dbus0_ acs_ miss_ cnt - L2-Cache bus0 Miss-Access Counter register
- l2_
dbus0_ acs_ nxtlvl_ rd_ cnt - L2-Cache bus0 Next-Level-Access Counter register
- l2_
dbus0_ acs_ nxtlvl_ wr_ cnt - L2-Cache bus0 WB-Access Counter register
- l2_
dbus1_ acs_ conflict_ cnt - L2-Cache bus1 Conflict-Access Counter register
- l2_
dbus1_ acs_ hit_ cnt - L2-Cache bus1 Hit-Access Counter register
- l2_
dbus1_ acs_ miss_ cnt - L2-Cache bus1 Miss-Access Counter register
- l2_
dbus1_ acs_ nxtlvl_ rd_ cnt - L2-Cache bus1 Next-Level-Access Counter register
- l2_
dbus1_ acs_ nxtlvl_ wr_ cnt - L2-Cache bus1 WB-Access Counter register
- l2_
dbus2_ acs_ conflict_ cnt - L2-Cache bus2 Conflict-Access Counter register
- l2_
dbus2_ acs_ hit_ cnt - L2-Cache bus2 Hit-Access Counter register
- l2_
dbus2_ acs_ miss_ cnt - L2-Cache bus2 Miss-Access Counter register
- l2_
dbus2_ acs_ nxtlvl_ rd_ cnt - L2-Cache bus2 Next-Level-Access Counter register
- l2_
dbus2_ acs_ nxtlvl_ wr_ cnt - L2-Cache bus2 WB-Access Counter register
- l2_
dbus3_ acs_ conflict_ cnt - L2-Cache bus3 Conflict-Access Counter register
- l2_
dbus3_ acs_ hit_ cnt - L2-Cache bus3 Hit-Access Counter register
- l2_
dbus3_ acs_ miss_ cnt - L2-Cache bus3 Miss-Access Counter register
- l2_
dbus3_ acs_ nxtlvl_ rd_ cnt - L2-Cache bus3 Next-Level-Access Counter register
- l2_
dbus3_ acs_ nxtlvl_ wr_ cnt - L2-Cache bus3 WB-Access Counter register
- l2_
ibus0_ acs_ conflict_ cnt - L2-Cache bus0 Conflict-Access Counter register
- l2_
ibus0_ acs_ hit_ cnt - L2-Cache bus0 Hit-Access Counter register
- l2_
ibus0_ acs_ miss_ cnt - L2-Cache bus0 Miss-Access Counter register
- l2_
ibus0_ acs_ nxtlvl_ rd_ cnt - L2-Cache bus0 Next-Level-Access Counter register
- l2_
ibus1_ acs_ conflict_ cnt - L2-Cache bus1 Conflict-Access Counter register
- l2_
ibus1_ acs_ hit_ cnt - L2-Cache bus1 Hit-Access Counter register
- l2_
ibus1_ acs_ miss_ cnt - L2-Cache bus1 Miss-Access Counter register
- l2_
ibus1_ acs_ nxtlvl_ rd_ cnt - L2-Cache bus1 Next-Level-Access Counter register
- l2_
ibus2_ acs_ conflict_ cnt - L2-Cache bus2 Conflict-Access Counter register
- l2_
ibus2_ acs_ hit_ cnt - L2-Cache bus2 Hit-Access Counter register
- l2_
ibus2_ acs_ miss_ cnt - L2-Cache bus2 Miss-Access Counter register
- l2_
ibus2_ acs_ nxtlvl_ rd_ cnt - L2-Cache bus2 Next-Level-Access Counter register
- l2_
ibus3_ acs_ conflict_ cnt - L2-Cache bus3 Conflict-Access Counter register
- l2_
ibus3_ acs_ hit_ cnt - L2-Cache bus3 Hit-Access Counter register
- l2_
ibus3_ acs_ miss_ cnt - L2-Cache bus3 Miss-Access Counter register
- l2_
ibus3_ acs_ nxtlvl_ rd_ cnt - L2-Cache bus3 Next-Level-Access Counter register
- l2_
unallocate_ buffer_ clear - Unallocate request buffer clear registers
- level_
split0 - USED TO SPLIT L1 CACHE AND L2 CACHE
- level_
split1 - USED TO SPLIT L1 CACHE AND L2 CACHE
- lock_
addr - Lock (manual lock) address configure register
- lock_
ctrl - Lock-class (manual lock) operation control register
- lock_
map - Lock (manual lock) map configure register
- lock_
size - Lock (manual lock) size configure register
- redundancy_
sig0 - Cache redundancy signal 0 register
- redundancy_
sig1 - Cache redundancy signal 1 register
- redundancy_
sig2 - Cache redundancy signal 2 register
- redundancy_
sig3 - Cache redundancy signal 3 register
- redundancy_
sig4 - Cache redundancy signal 0 register
- sync_
addr - Sync address configure register
- sync_
ctrl - Sync-class operation control register
- sync_
l1_ cache_ preload_ exception - Cache Sync/Preload Operation exception register
- sync_
l1_ cache_ preload_ int_ clr - Sync Preload operation Interrupt clear register
- sync_
l1_ cache_ preload_ int_ ena - L1-Cache Access Fail Interrupt enable register
- sync_
l1_ cache_ preload_ int_ raw - Sync Preload operation Interrupt raw register
- sync_
l1_ cache_ preload_ int_ st - L1-Cache Access Fail Interrupt status register
- sync_
map - Sync map configure register
- sync_
size - Sync size configure register
Structsยง
- Register
Block - Register block
Type Aliasesยง
- CLOCK_
GATE - CLOCK_GATE (rw) register accessor: Clock gate control register
- DATE
- DATE (rw) register accessor: Version control register
- L1_
BYPASS_ CACHE_ CONF - L1_BYPASS_CACHE_CONF (rw) register accessor: Bypass Cache configure register
- L1_
CACHE_ ACS_ CNT_ CTRL - L1_CACHE_ACS_CNT_CTRL (rw) register accessor: Cache Access Counter enable and clear register
- L1_
CACHE_ ACS_ CNT_ INT_ CLR - L1_CACHE_ACS_CNT_INT_CLR (rw) register accessor: Cache Access Counter Interrupt clear register
- L1_
CACHE_ ACS_ CNT_ INT_ ENA - L1_CACHE_ACS_CNT_INT_ENA (rw) register accessor: Cache Access Counter Interrupt enable register
- L1_
CACHE_ ACS_ CNT_ INT_ RAW - L1_CACHE_ACS_CNT_INT_RAW (rw) register accessor: Cache Access Counter Interrupt raw register
- L1_
CACHE_ ACS_ CNT_ INT_ ST - L1_CACHE_ACS_CNT_INT_ST (r) register accessor: Cache Access Counter Interrupt status register
- L1_
CACHE_ ACS_ FAIL_ CTRL - L1_CACHE_ACS_FAIL_CTRL (rw) register accessor: Cache Access Fail Configuration register
- L1_
CACHE_ ACS_ FAIL_ INT_ CLR - L1_CACHE_ACS_FAIL_INT_CLR (rw) register accessor: L1-Cache Access Fail Interrupt clear register
- L1_
CACHE_ ACS_ FAIL_ INT_ ENA - L1_CACHE_ACS_FAIL_INT_ENA (rw) register accessor: Cache Access Fail Interrupt enable register
- L1_
CACHE_ ACS_ FAIL_ INT_ RAW - L1_CACHE_ACS_FAIL_INT_RAW (rw) register accessor: Cache Access Fail Interrupt raw register
- L1_
CACHE_ ACS_ FAIL_ INT_ ST - L1_CACHE_ACS_FAIL_INT_ST (r) register accessor: Cache Access Fail Interrupt status register
- L1_
CACHE_ ATOMIC_ CONF - L1_CACHE_ATOMIC_CONF (rw) register accessor: L1 Cache atomic feature configure register
- L1_
CACHE_ AUTOLOAD_ BUF_ CLR_ CTRL - L1_CACHE_AUTOLOAD_BUF_CLR_CTRL (rw) register accessor: Cache Autoload buffer clear control register
- L1_
CACHE_ DATA_ MEM_ ACS_ CONF - L1_CACHE_DATA_MEM_ACS_CONF (rw) register accessor: Cache data memory access configure register
- L1_
CACHE_ DATA_ MEM_ POWER_ CTRL - L1_CACHE_DATA_MEM_POWER_CTRL (rw) register accessor: Cache data memory power control register
- L1_
CACHE_ DEBUG_ BUS - L1_CACHE_DEBUG_BUS (rw) register accessor: Cache Tag/data memory content register
- L1_
CACHE_ FREEZE_ CTRL - L1_CACHE_FREEZE_CTRL (rw) register accessor: Cache Freeze control register
- L1_
CACHE_ OBJECT_ CTRL - L1_CACHE_OBJECT_CTRL (rw) register accessor: Cache Tag and Data memory Object control register
- L1_
CACHE_ PRELOAD_ RST_ CTRL - L1_CACHE_PRELOAD_RST_CTRL (rw) register accessor: Cache Preload Reset control register
- L1_
CACHE_ SYNC_ RST_ CTRL - L1_CACHE_SYNC_RST_CTRL (rw) register accessor: Cache Sync Reset control register
- L1_
CACHE_ TAG_ MEM_ ACS_ CONF - L1_CACHE_TAG_MEM_ACS_CONF (rw) register accessor: Cache tag memory access configure register
- L1_
CACHE_ TAG_ MEM_ POWER_ CTRL - L1_CACHE_TAG_MEM_POWER_CTRL (rw) register accessor: Cache tag memory power control register
- L1_
CACHE_ VADDR - L1_CACHE_VADDR (rw) register accessor: Cache Vaddr register
- L1_
CACHE_ WAY_ OBJECT - L1_CACHE_WAY_OBJECT (rw) register accessor: Cache Tag and Data memory way register
- L1_
CACHE_ WRAP_ AROUND_ CTRL - L1_CACHE_WRAP_AROUND_CTRL (rw) register accessor: Cache wrap around control register
- L1_
DBUS0_ ACS_ CONFLICT_ CNT - L1_DBUS0_ACS_CONFLICT_CNT (r) register accessor: L1-DCache bus0 Conflict-Access Counter register
- L1_
DBUS0_ ACS_ HIT_ CNT - L1_DBUS0_ACS_HIT_CNT (r) register accessor: L1-DCache bus0 Hit-Access Counter register
- L1_
DBUS0_ ACS_ MISS_ CNT - L1_DBUS0_ACS_MISS_CNT (r) register accessor: L1-DCache bus0 Miss-Access Counter register
- L1_
DBUS0_ ACS_ NXTLVL_ RD_ CNT - L1_DBUS0_ACS_NXTLVL_RD_CNT (r) register accessor: L1-DCache bus0 Next-Level-Access Counter register
- L1_
DBUS0_ ACS_ NXTLVL_ WR_ CNT - L1_DBUS0_ACS_NXTLVL_WR_CNT (r) register accessor: L1-DCache bus0 WB-Access Counter register
- L1_
DBUS1_ ACS_ CONFLICT_ CNT - L1_DBUS1_ACS_CONFLICT_CNT (r) register accessor: L1-DCache bus1 Conflict-Access Counter register
- L1_
DBUS1_ ACS_ HIT_ CNT - L1_DBUS1_ACS_HIT_CNT (r) register accessor: L1-DCache bus1 Hit-Access Counter register
- L1_
DBUS1_ ACS_ MISS_ CNT - L1_DBUS1_ACS_MISS_CNT (r) register accessor: L1-DCache bus1 Miss-Access Counter register
- L1_
DBUS1_ ACS_ NXTLVL_ RD_ CNT - L1_DBUS1_ACS_NXTLVL_RD_CNT (r) register accessor: L1-DCache bus1 Next-Level-Access Counter register
- L1_
DBUS1_ ACS_ NXTLVL_ WR_ CNT - L1_DBUS1_ACS_NXTLVL_WR_CNT (r) register accessor: L1-DCache bus1 WB-Access Counter register
- L1_
DBUS2_ ACS_ CONFLICT_ CNT - L1_DBUS2_ACS_CONFLICT_CNT (r) register accessor: L1-DCache bus2 Conflict-Access Counter register
- L1_
DBUS2_ ACS_ HIT_ CNT - L1_DBUS2_ACS_HIT_CNT (r) register accessor: L1-DCache bus2 Hit-Access Counter register
- L1_
DBUS2_ ACS_ MISS_ CNT - L1_DBUS2_ACS_MISS_CNT (r) register accessor: L1-DCache bus2 Miss-Access Counter register
- L1_
DBUS2_ ACS_ NXTLVL_ RD_ CNT - L1_DBUS2_ACS_NXTLVL_RD_CNT (r) register accessor: L1-DCache bus2 Next-Level-Access Counter register
- L1_
DBUS2_ ACS_ NXTLVL_ WR_ CNT - L1_DBUS2_ACS_NXTLVL_WR_CNT (r) register accessor: L1-DCache bus2 WB-Access Counter register
- L1_
DBUS3_ ACS_ CONFLICT_ CNT - L1_DBUS3_ACS_CONFLICT_CNT (r) register accessor: L1-DCache bus3 Conflict-Access Counter register
- L1_
DBUS3_ ACS_ HIT_ CNT - L1_DBUS3_ACS_HIT_CNT (r) register accessor: L1-DCache bus3 Hit-Access Counter register
- L1_
DBUS3_ ACS_ MISS_ CNT - L1_DBUS3_ACS_MISS_CNT (r) register accessor: L1-DCache bus3 Miss-Access Counter register
- L1_
DBUS3_ ACS_ NXTLVL_ RD_ CNT - L1_DBUS3_ACS_NXTLVL_RD_CNT (r) register accessor: L1-DCache bus3 Next-Level-Access Counter register
- L1_
DBUS3_ ACS_ NXTLVL_ WR_ CNT - L1_DBUS3_ACS_NXTLVL_WR_CNT (r) register accessor: L1-DCache bus3 WB-Access Counter register
- L1_
DCACHE_ ACS_ FAIL_ ADDR - L1_DCACHE_ACS_FAIL_ADDR (r) register accessor: L1-DCache Access Fail Address information register
- L1_
DCACHE_ ACS_ FAIL_ ID_ ATTR - L1_DCACHE_ACS_FAIL_ID_ATTR (r) register accessor: L1-DCache Access Fail ID/attribution information register
- L1_
DCACHE_ AUTOLOAD_ CTRL - L1_DCACHE_AUTOLOAD_CTRL (rw) register accessor: L1 data Cache autoload-operation control register
- L1_
DCACHE_ AUTOLOAD_ SCT0_ ADDR - L1_DCACHE_AUTOLOAD_SCT0_ADDR (rw) register accessor: L1 data Cache autoload section 0 address configure register
- L1_
DCACHE_ AUTOLOAD_ SCT0_ SIZE - L1_DCACHE_AUTOLOAD_SCT0_SIZE (rw) register accessor: L1 data Cache autoload section 0 size configure register
- L1_
DCACHE_ AUTOLOAD_ SCT1_ ADDR - L1_DCACHE_AUTOLOAD_SCT1_ADDR (rw) register accessor: L1 data Cache autoload section 1 address configure register
- L1_
DCACHE_ AUTOLOAD_ SCT1_ SIZE - L1_DCACHE_AUTOLOAD_SCT1_SIZE (rw) register accessor: L1 data Cache autoload section 1 size configure register
- L1_
DCACHE_ AUTOLOAD_ SCT2_ ADDR - L1_DCACHE_AUTOLOAD_SCT2_ADDR (rw) register accessor: L1 data Cache autoload section 2 address configure register
- L1_
DCACHE_ AUTOLOAD_ SCT2_ SIZE - L1_DCACHE_AUTOLOAD_SCT2_SIZE (rw) register accessor: L1 data Cache autoload section 2 size configure register
- L1_
DCACHE_ AUTOLOAD_ SCT3_ ADDR - L1_DCACHE_AUTOLOAD_SCT3_ADDR (rw) register accessor: L1 data Cache autoload section 1 address configure register
- L1_
DCACHE_ AUTOLOAD_ SCT3_ SIZE - L1_DCACHE_AUTOLOAD_SCT3_SIZE (rw) register accessor: L1 data Cache autoload section 1 size configure register
- L1_
DCACHE_ BLOCKSIZE_ CONF - L1_DCACHE_BLOCKSIZE_CONF (r) register accessor: L1 data Cache BlockSize mode configure register
- L1_
DCACHE_ CACHESIZE_ CONF - L1_DCACHE_CACHESIZE_CONF (r) register accessor: L1 data Cache CacheSize mode configure register
- L1_
DCACHE_ CTRL - L1_DCACHE_CTRL (rw) register accessor: L1 data Cache(L1-DCache) control register
- L1_
DCACHE_ PRELOAD_ ADDR - L1_DCACHE_PRELOAD_ADDR (rw) register accessor: L1 data Cache preload address configure register
- L1_
DCACHE_ PRELOAD_ CTRL - L1_DCACHE_PRELOAD_CTRL (rw) register accessor: L1 data Cache preload-operation control register
- L1_
DCACHE_ PRELOAD_ SIZE - L1_DCACHE_PRELOAD_SIZE (rw) register accessor: L1 data Cache preload size configure register
- L1_
DCACHE_ PRELOCK_ CONF - L1_DCACHE_PRELOCK_CONF (rw) register accessor: L1 data Cache prelock configure register
- L1_
DCACHE_ PRELOCK_ SCT0_ ADDR - L1_DCACHE_PRELOCK_SCT0_ADDR (rw) register accessor: L1 data Cache prelock section0 address configure register
- L1_
DCACHE_ PRELOCK_ SCT1_ ADDR - L1_DCACHE_PRELOCK_SCT1_ADDR (rw) register accessor: L1 data Cache prelock section1 address configure register
- L1_
DCACHE_ PRELOCK_ SCT_ SIZE - L1_DCACHE_PRELOCK_SCT_SIZE (rw) register accessor: L1 data Cache prelock section size configure register
- L1_
IBUS0_ ACS_ CONFLICT_ CNT - L1_IBUS0_ACS_CONFLICT_CNT (r) register accessor: L1-ICache bus0 Conflict-Access Counter register
- L1_
IBUS0_ ACS_ HIT_ CNT - L1_IBUS0_ACS_HIT_CNT (r) register accessor: L1-ICache bus0 Hit-Access Counter register
- L1_
IBUS0_ ACS_ MISS_ CNT - L1_IBUS0_ACS_MISS_CNT (r) register accessor: L1-ICache bus0 Miss-Access Counter register
- L1_
IBUS0_ ACS_ NXTLVL_ RD_ CNT - L1_IBUS0_ACS_NXTLVL_RD_CNT (r) register accessor: L1-ICache bus0 Next-Level-Access Counter register
- L1_
IBUS1_ ACS_ CONFLICT_ CNT - L1_IBUS1_ACS_CONFLICT_CNT (r) register accessor: L1-ICache bus1 Conflict-Access Counter register
- L1_
IBUS1_ ACS_ HIT_ CNT - L1_IBUS1_ACS_HIT_CNT (r) register accessor: L1-ICache bus1 Hit-Access Counter register
- L1_
IBUS1_ ACS_ MISS_ CNT - L1_IBUS1_ACS_MISS_CNT (r) register accessor: L1-ICache bus1 Miss-Access Counter register
- L1_
IBUS1_ ACS_ NXTLVL_ RD_ CNT - L1_IBUS1_ACS_NXTLVL_RD_CNT (r) register accessor: L1-ICache bus1 Next-Level-Access Counter register
- L1_
IBUS2_ ACS_ CONFLICT_ CNT - L1_IBUS2_ACS_CONFLICT_CNT (r) register accessor: L1-ICache bus2 Conflict-Access Counter register
- L1_
IBUS2_ ACS_ HIT_ CNT - L1_IBUS2_ACS_HIT_CNT (r) register accessor: L1-ICache bus2 Hit-Access Counter register
- L1_
IBUS2_ ACS_ MISS_ CNT - L1_IBUS2_ACS_MISS_CNT (r) register accessor: L1-ICache bus2 Miss-Access Counter register
- L1_
IBUS2_ ACS_ NXTLVL_ RD_ CNT - L1_IBUS2_ACS_NXTLVL_RD_CNT (r) register accessor: L1-ICache bus2 Next-Level-Access Counter register
- L1_
IBUS3_ ACS_ CONFLICT_ CNT - L1_IBUS3_ACS_CONFLICT_CNT (r) register accessor: L1-ICache bus3 Conflict-Access Counter register
- L1_
IBUS3_ ACS_ HIT_ CNT - L1_IBUS3_ACS_HIT_CNT (r) register accessor: L1-ICache bus3 Hit-Access Counter register
- L1_
IBUS3_ ACS_ MISS_ CNT - L1_IBUS3_ACS_MISS_CNT (r) register accessor: L1-ICache bus3 Miss-Access Counter register
- L1_
IBUS3_ ACS_ NXTLVL_ RD_ CNT - L1_IBUS3_ACS_NXTLVL_RD_CNT (r) register accessor: L1-ICache bus3 Next-Level-Access Counter register
- L1_
ICACH E0_ ACS_ FAIL_ ADDR - L1_ICACHE0_ACS_FAIL_ADDR (r) register accessor: L1-ICache0 Access Fail Address information register
- L1_
ICACH E0_ ACS_ FAIL_ ID_ ATTR - L1_ICACHE0_ACS_FAIL_ID_ATTR (r) register accessor: L1-ICache0 Access Fail ID/attribution information register
- L1_
ICACH E0_ AUTOLOAD_ CTRL - L1_ICACHE0_AUTOLOAD_CTRL (rw) register accessor: L1 instruction Cache 0 autoload-operation control register
- L1_
ICACH E0_ AUTOLOAD_ SCT0_ ADDR - L1_ICACHE0_AUTOLOAD_SCT0_ADDR (rw) register accessor: L1 instruction Cache 0 autoload section 0 address configure register
- L1_
ICACH E0_ AUTOLOAD_ SCT0_ SIZE - L1_ICACHE0_AUTOLOAD_SCT0_SIZE (rw) register accessor: L1 instruction Cache 0 autoload section 0 size configure register
- L1_
ICACH E0_ AUTOLOAD_ SCT1_ ADDR - L1_ICACHE0_AUTOLOAD_SCT1_ADDR (rw) register accessor: L1 instruction Cache 0 autoload section 1 address configure register
- L1_
ICACH E0_ AUTOLOAD_ SCT1_ SIZE - L1_ICACHE0_AUTOLOAD_SCT1_SIZE (rw) register accessor: L1 instruction Cache 0 autoload section 1 size configure register
- L1_
ICACH E0_ PRELOAD_ ADDR - L1_ICACHE0_PRELOAD_ADDR (rw) register accessor: L1 instruction Cache 0 preload address configure register
- L1_
ICACH E0_ PRELOAD_ CTRL - L1_ICACHE0_PRELOAD_CTRL (rw) register accessor: L1 instruction Cache 0 preload-operation control register
- L1_
ICACH E0_ PRELOAD_ SIZE - L1_ICACHE0_PRELOAD_SIZE (rw) register accessor: L1 instruction Cache 0 preload size configure register
- L1_
ICACH E0_ PRELOCK_ CONF - L1_ICACHE0_PRELOCK_CONF (rw) register accessor: L1 instruction Cache 0 prelock configure register
- L1_
ICACH E0_ PRELOCK_ SCT0_ ADDR - L1_ICACHE0_PRELOCK_SCT0_ADDR (rw) register accessor: L1 instruction Cache 0 prelock section0 address configure register
- L1_
ICACH E0_ PRELOCK_ SCT1_ ADDR - L1_ICACHE0_PRELOCK_SCT1_ADDR (rw) register accessor: L1 instruction Cache 0 prelock section1 address configure register
- L1_
ICACH E0_ PRELOCK_ SCT_ SIZE - L1_ICACHE0_PRELOCK_SCT_SIZE (rw) register accessor: L1 instruction Cache 0 prelock section size configure register
- L1_
ICACH E1_ ACS_ FAIL_ ADDR - L1_ICACHE1_ACS_FAIL_ADDR (r) register accessor: L1-ICache0 Access Fail Address information register
- L1_
ICACH E1_ ACS_ FAIL_ ID_ ATTR - L1_ICACHE1_ACS_FAIL_ID_ATTR (r) register accessor: L1-ICache0 Access Fail ID/attribution information register
- L1_
ICACH E1_ AUTOLOAD_ CTRL - L1_ICACHE1_AUTOLOAD_CTRL (rw) register accessor: L1 instruction Cache 1 autoload-operation control register
- L1_
ICACH E1_ AUTOLOAD_ SCT0_ ADDR - L1_ICACHE1_AUTOLOAD_SCT0_ADDR (rw) register accessor: L1 instruction Cache 1 autoload section 0 address configure register
- L1_
ICACH E1_ AUTOLOAD_ SCT0_ SIZE - L1_ICACHE1_AUTOLOAD_SCT0_SIZE (rw) register accessor: L1 instruction Cache 1 autoload section 0 size configure register
- L1_
ICACH E1_ AUTOLOAD_ SCT1_ ADDR - L1_ICACHE1_AUTOLOAD_SCT1_ADDR (rw) register accessor: L1 instruction Cache 1 autoload section 1 address configure register
- L1_
ICACH E1_ AUTOLOAD_ SCT1_ SIZE - L1_ICACHE1_AUTOLOAD_SCT1_SIZE (rw) register accessor: L1 instruction Cache 1 autoload section 1 size configure register
- L1_
ICACH E1_ PRELOAD_ ADDR - L1_ICACHE1_PRELOAD_ADDR (rw) register accessor: L1 instruction Cache 1 preload address configure register
- L1_
ICACH E1_ PRELOAD_ CTRL - L1_ICACHE1_PRELOAD_CTRL (rw) register accessor: L1 instruction Cache 1 preload-operation control register
- L1_
ICACH E1_ PRELOAD_ SIZE - L1_ICACHE1_PRELOAD_SIZE (rw) register accessor: L1 instruction Cache 1 preload size configure register
- L1_
ICACH E1_ PRELOCK_ CONF - L1_ICACHE1_PRELOCK_CONF (rw) register accessor: L1 instruction Cache 1 prelock configure register
- L1_
ICACH E1_ PRELOCK_ SCT0_ ADDR - L1_ICACHE1_PRELOCK_SCT0_ADDR (rw) register accessor: L1 instruction Cache 1 prelock section0 address configure register
- L1_
ICACH E1_ PRELOCK_ SCT1_ ADDR - L1_ICACHE1_PRELOCK_SCT1_ADDR (rw) register accessor: L1 instruction Cache 1 prelock section1 address configure register
- L1_
ICACH E1_ PRELOCK_ SCT_ SIZE - L1_ICACHE1_PRELOCK_SCT_SIZE (rw) register accessor: L1 instruction Cache 1 prelock section size configure register
- L1_
ICACH E2_ ACS_ FAIL_ ADDR - L1_ICACHE2_ACS_FAIL_ADDR (r) register accessor: L1-ICache0 Access Fail Address information register
- L1_
ICACH E2_ ACS_ FAIL_ ID_ ATTR - L1_ICACHE2_ACS_FAIL_ID_ATTR (r) register accessor: L1-ICache0 Access Fail ID/attribution information register
- L1_
ICACH E2_ AUTOLOAD_ CTRL - L1_ICACHE2_AUTOLOAD_CTRL (r) register accessor: L1 instruction Cache 2 autoload-operation control register
- L1_
ICACH E2_ AUTOLOAD_ SCT0_ ADDR - L1_ICACHE2_AUTOLOAD_SCT0_ADDR (r) register accessor: L1 instruction Cache 2 autoload section 0 address configure register
- L1_
ICACH E2_ AUTOLOAD_ SCT0_ SIZE - L1_ICACHE2_AUTOLOAD_SCT0_SIZE (r) register accessor: L1 instruction Cache 2 autoload section 0 size configure register
- L1_
ICACH E2_ AUTOLOAD_ SCT1_ ADDR - L1_ICACHE2_AUTOLOAD_SCT1_ADDR (r) register accessor: L1 instruction Cache 2 autoload section 1 address configure register
- L1_
ICACH E2_ AUTOLOAD_ SCT1_ SIZE - L1_ICACHE2_AUTOLOAD_SCT1_SIZE (r) register accessor: L1 instruction Cache 2 autoload section 1 size configure register
- L1_
ICACH E2_ PRELOAD_ ADDR - L1_ICACHE2_PRELOAD_ADDR (r) register accessor: L1 instruction Cache 2 preload address configure register
- L1_
ICACH E2_ PRELOAD_ CTRL - L1_ICACHE2_PRELOAD_CTRL (r) register accessor: L1 instruction Cache 2 preload-operation control register
- L1_
ICACH E2_ PRELOAD_ SIZE - L1_ICACHE2_PRELOAD_SIZE (r) register accessor: L1 instruction Cache 2 preload size configure register
- L1_
ICACH E2_ PRELOCK_ CONF - L1_ICACHE2_PRELOCK_CONF (r) register accessor: L1 instruction Cache 2 prelock configure register
- L1_
ICACH E2_ PRELOCK_ SCT0_ ADDR - L1_ICACHE2_PRELOCK_SCT0_ADDR (r) register accessor: L1 instruction Cache 2 prelock section0 address configure register
- L1_
ICACH E2_ PRELOCK_ SCT1_ ADDR - L1_ICACHE2_PRELOCK_SCT1_ADDR (r) register accessor: L1 instruction Cache 2 prelock section1 address configure register
- L1_
ICACH E2_ PRELOCK_ SCT_ SIZE - L1_ICACHE2_PRELOCK_SCT_SIZE (r) register accessor: L1 instruction Cache 2 prelock section size configure register
- L1_
ICACH E3_ ACS_ FAIL_ ADDR - L1_ICACHE3_ACS_FAIL_ADDR (r) register accessor: L1-ICache0 Access Fail Address information register
- L1_
ICACH E3_ ACS_ FAIL_ ID_ ATTR - L1_ICACHE3_ACS_FAIL_ID_ATTR (r) register accessor: L1-ICache0 Access Fail ID/attribution information register
- L1_
ICACH E3_ AUTOLOAD_ CTRL - L1_ICACHE3_AUTOLOAD_CTRL (r) register accessor: L1 instruction Cache 3 autoload-operation control register
- L1_
ICACH E3_ AUTOLOAD_ SCT0_ ADDR - L1_ICACHE3_AUTOLOAD_SCT0_ADDR (r) register accessor: L1 instruction Cache 3 autoload section 0 address configure register
- L1_
ICACH E3_ AUTOLOAD_ SCT0_ SIZE - L1_ICACHE3_AUTOLOAD_SCT0_SIZE (r) register accessor: L1 instruction Cache 3 autoload section 0 size configure register
- L1_
ICACH E3_ AUTOLOAD_ SCT1_ ADDR - L1_ICACHE3_AUTOLOAD_SCT1_ADDR (r) register accessor: L1 instruction Cache 3 autoload section 1 address configure register
- L1_
ICACH E3_ AUTOLOAD_ SCT1_ SIZE - L1_ICACHE3_AUTOLOAD_SCT1_SIZE (r) register accessor: L1 instruction Cache 3 autoload section 1 size configure register
- L1_
ICACH E3_ PRELOAD_ ADDR - L1_ICACHE3_PRELOAD_ADDR (r) register accessor: L1 instruction Cache 3 preload address configure register
- L1_
ICACH E3_ PRELOAD_ CTRL - L1_ICACHE3_PRELOAD_CTRL (r) register accessor: L1 instruction Cache 3 preload-operation control register
- L1_
ICACH E3_ PRELOAD_ SIZE - L1_ICACHE3_PRELOAD_SIZE (r) register accessor: L1 instruction Cache 3 preload size configure register
- L1_
ICACH E3_ PRELOCK_ CONF - L1_ICACHE3_PRELOCK_CONF (r) register accessor: L1 instruction Cache 3 prelock configure register
- L1_
ICACH E3_ PRELOCK_ SCT0_ ADDR - L1_ICACHE3_PRELOCK_SCT0_ADDR (r) register accessor: L1 instruction Cache 3 prelock section0 address configure register
- L1_
ICACH E3_ PRELOCK_ SCT1_ ADDR - L1_ICACHE3_PRELOCK_SCT1_ADDR (r) register accessor: L1 instruction Cache 3 prelock section1 address configure register
- L1_
ICACH E3_ PRELOCK_ SCT_ SIZE - L1_ICACHE3_PRELOCK_SCT_SIZE (r) register accessor: L1 instruction Cache 3 prelock section size configure register
- L1_
ICACHE_ BLOCKSIZE_ CONF - L1_ICACHE_BLOCKSIZE_CONF (r) register accessor: L1 instruction Cache BlockSize mode configure register
- L1_
ICACHE_ CACHESIZE_ CONF - L1_ICACHE_CACHESIZE_CONF (r) register accessor: L1 instruction Cache CacheSize mode configure register
- L1_
ICACHE_ CTRL - L1_ICACHE_CTRL (rw) register accessor: L1 instruction Cache(L1-ICache) control register
- L1_
UNALLOCATE_ BUFFER_ CLEAR - L1_UNALLOCATE_BUFFER_CLEAR (rw) register accessor: Unallocate request buffer clear registers
- L2_
BYPASS_ CACHE_ CONF - L2_BYPASS_CACHE_CONF (rw) register accessor: Bypass Cache configure register
- L2_
CACHE_ ACCESS_ ATTR_ CTRL - L2_CACHE_ACCESS_ATTR_CTRL (rw) register accessor: L2 cache access attribute control register
- L2_
CACHE_ ACS_ CNT_ CTRL - L2_CACHE_ACS_CNT_CTRL (rw) register accessor: Cache Access Counter enable and clear register
- L2_
CACHE_ ACS_ CNT_ INT_ CLR - L2_CACHE_ACS_CNT_INT_CLR (rw) register accessor: Cache Access Counter Interrupt clear register
- L2_
CACHE_ ACS_ CNT_ INT_ ENA - L2_CACHE_ACS_CNT_INT_ENA (rw) register accessor: Cache Access Counter Interrupt enable register
- L2_
CACHE_ ACS_ CNT_ INT_ RAW - L2_CACHE_ACS_CNT_INT_RAW (rw) register accessor: Cache Access Counter Interrupt raw register
- L2_
CACHE_ ACS_ CNT_ INT_ ST - L2_CACHE_ACS_CNT_INT_ST (r) register accessor: Cache Access Counter Interrupt status register
- L2_
CACHE_ ACS_ FAIL_ ADDR - L2_CACHE_ACS_FAIL_ADDR (r) register accessor: L2-Cache Access Fail Address information register
- L2_
CACHE_ ACS_ FAIL_ CTRL - L2_CACHE_ACS_FAIL_CTRL (rw) register accessor: Cache Access Fail Configuration register
- L2_
CACHE_ ACS_ FAIL_ ID_ ATTR - L2_CACHE_ACS_FAIL_ID_ATTR (r) register accessor: L2-Cache Access Fail ID/attribution information register
- L2_
CACHE_ ACS_ FAIL_ INT_ CLR - L2_CACHE_ACS_FAIL_INT_CLR (w) register accessor: L1-Cache Access Fail Interrupt clear register
- L2_
CACHE_ ACS_ FAIL_ INT_ ENA - L2_CACHE_ACS_FAIL_INT_ENA (rw) register accessor: Cache Access Fail Interrupt enable register
- L2_
CACHE_ ACS_ FAIL_ INT_ RAW - L2_CACHE_ACS_FAIL_INT_RAW (rw) register accessor: Cache Access Fail Interrupt raw register
- L2_
CACHE_ ACS_ FAIL_ INT_ ST - L2_CACHE_ACS_FAIL_INT_ST (r) register accessor: Cache Access Fail Interrupt status register
- L2_
CACHE_ AUTOLOAD_ BUF_ CLR_ CTRL - L2_CACHE_AUTOLOAD_BUF_CLR_CTRL (rw) register accessor: Cache Autoload buffer clear control register
- L2_
CACHE_ AUTOLOAD_ CTRL - L2_CACHE_AUTOLOAD_CTRL (rw) register accessor: L2 Cache autoload-operation control register
- L2_
CACHE_ AUTOLOAD_ SCT0_ ADDR - L2_CACHE_AUTOLOAD_SCT0_ADDR (rw) register accessor: L2 Cache autoload section 0 address configure register
- L2_
CACHE_ AUTOLOAD_ SCT0_ SIZE - L2_CACHE_AUTOLOAD_SCT0_SIZE (rw) register accessor: L2 Cache autoload section 0 size configure register
- L2_
CACHE_ AUTOLOAD_ SCT1_ ADDR - L2_CACHE_AUTOLOAD_SCT1_ADDR (rw) register accessor: L2 Cache autoload section 1 address configure register
- L2_
CACHE_ AUTOLOAD_ SCT1_ SIZE - L2_CACHE_AUTOLOAD_SCT1_SIZE (rw) register accessor: L2 Cache autoload section 1 size configure register
- L2_
CACHE_ AUTOLOAD_ SCT2_ ADDR - L2_CACHE_AUTOLOAD_SCT2_ADDR (rw) register accessor: L2 Cache autoload section 2 address configure register
- L2_
CACHE_ AUTOLOAD_ SCT2_ SIZE - L2_CACHE_AUTOLOAD_SCT2_SIZE (rw) register accessor: L2 Cache autoload section 2 size configure register
- L2_
CACHE_ AUTOLOAD_ SCT3_ ADDR - L2_CACHE_AUTOLOAD_SCT3_ADDR (rw) register accessor: L2 Cache autoload section 3 address configure register
- L2_
CACHE_ AUTOLOAD_ SCT3_ SIZE - L2_CACHE_AUTOLOAD_SCT3_SIZE (rw) register accessor: L2 Cache autoload section 3 size configure register
- L2_
CACHE_ BLOCKSIZE_ CONF - L2_CACHE_BLOCKSIZE_CONF (rw) register accessor: L2 Cache BlockSize mode configure register
- L2_
CACHE_ CACHESIZE_ CONF - L2_CACHE_CACHESIZE_CONF (rw) register accessor: L2 Cache CacheSize mode configure register
- L2_
CACHE_ CTRL - L2_CACHE_CTRL (rw) register accessor: L2 Cache(L2-Cache) control register
- L2_
CACHE_ DATA_ MEM_ ACS_ CONF - L2_CACHE_DATA_MEM_ACS_CONF (rw) register accessor: Cache data memory access configure register
- L2_
CACHE_ DATA_ MEM_ POWER_ CTRL - L2_CACHE_DATA_MEM_POWER_CTRL (rw) register accessor: Cache data memory power control register
- L2_
CACHE_ DEBUG_ BUS - L2_CACHE_DEBUG_BUS (rw) register accessor: Cache Tag/data memory content register
- L2_
CACHE_ FREEZE_ CTRL - L2_CACHE_FREEZE_CTRL (rw) register accessor: Cache Freeze control register
- L2_
CACHE_ OBJECT_ CTRL - L2_CACHE_OBJECT_CTRL (rw) register accessor: Cache Tag and Data memory Object control register
- L2_
CACHE_ PRELOAD_ ADDR - L2_CACHE_PRELOAD_ADDR (rw) register accessor: L2 Cache preload address configure register
- L2_
CACHE_ PRELOAD_ CTRL - L2_CACHE_PRELOAD_CTRL (rw) register accessor: L2 Cache preload-operation control register
- L2_
CACHE_ PRELOAD_ RST_ CTRL - L2_CACHE_PRELOAD_RST_CTRL (rw) register accessor: Cache Preload Reset control register
- L2_
CACHE_ PRELOAD_ SIZE - L2_CACHE_PRELOAD_SIZE (rw) register accessor: L2 Cache preload size configure register
- L2_
CACHE_ PRELOCK_ CONF - L2_CACHE_PRELOCK_CONF (rw) register accessor: L2 Cache prelock configure register
- L2_
CACHE_ PRELOCK_ SCT0_ ADDR - L2_CACHE_PRELOCK_SCT0_ADDR (rw) register accessor: L2 Cache prelock section0 address configure register
- L2_
CACHE_ PRELOCK_ SCT1_ ADDR - L2_CACHE_PRELOCK_SCT1_ADDR (rw) register accessor: L2 Cache prelock section1 address configure register
- L2_
CACHE_ PRELOCK_ SCT_ SIZE - L2_CACHE_PRELOCK_SCT_SIZE (rw) register accessor: L2 Cache prelock section size configure register
- L2_
CACHE_ SYNC_ PRELOAD_ EXCEPTION - L2_CACHE_SYNC_PRELOAD_EXCEPTION (r) register accessor: Cache Sync/Preload Operation exception register
- L2_
CACHE_ SYNC_ PRELOAD_ INT_ CLR - L2_CACHE_SYNC_PRELOAD_INT_CLR (w) register accessor: Sync Preload operation Interrupt clear register
- L2_
CACHE_ SYNC_ PRELOAD_ INT_ ENA - L2_CACHE_SYNC_PRELOAD_INT_ENA (rw) register accessor: L1-Cache Access Fail Interrupt enable register
- L2_
CACHE_ SYNC_ PRELOAD_ INT_ RAW - L2_CACHE_SYNC_PRELOAD_INT_RAW (rw) register accessor: Sync Preload operation Interrupt raw register
- L2_
CACHE_ SYNC_ PRELOAD_ INT_ ST - L2_CACHE_SYNC_PRELOAD_INT_ST (r) register accessor: L1-Cache Access Fail Interrupt status register
- L2_
CACHE_ SYNC_ RST_ CTRL - L2_CACHE_SYNC_RST_CTRL (rw) register accessor: Cache Sync Reset control register
- L2_
CACHE_ TAG_ MEM_ ACS_ CONF - L2_CACHE_TAG_MEM_ACS_CONF (rw) register accessor: Cache tag memory access configure register
- L2_
CACHE_ TAG_ MEM_ POWER_ CTRL - L2_CACHE_TAG_MEM_POWER_CTRL (rw) register accessor: Cache tag memory power control register
- L2_
CACHE_ VADDR - L2_CACHE_VADDR (rw) register accessor: Cache Vaddr register
- L2_
CACHE_ WAY_ OBJECT - L2_CACHE_WAY_OBJECT (rw) register accessor: Cache Tag and Data memory way register
- L2_
CACHE_ WRAP_ AROUND_ CTRL - L2_CACHE_WRAP_AROUND_CTRL (rw) register accessor: Cache wrap around control register
- L2_
DBUS0_ ACS_ CONFLICT_ CNT - L2_DBUS0_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus0 Conflict-Access Counter register
- L2_
DBUS0_ ACS_ HIT_ CNT - L2_DBUS0_ACS_HIT_CNT (r) register accessor: L2-Cache bus0 Hit-Access Counter register
- L2_
DBUS0_ ACS_ MISS_ CNT - L2_DBUS0_ACS_MISS_CNT (r) register accessor: L2-Cache bus0 Miss-Access Counter register
- L2_
DBUS0_ ACS_ NXTLVL_ RD_ CNT - L2_DBUS0_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus0 Next-Level-Access Counter register
- L2_
DBUS0_ ACS_ NXTLVL_ WR_ CNT - L2_DBUS0_ACS_NXTLVL_WR_CNT (r) register accessor: L2-Cache bus0 WB-Access Counter register
- L2_
DBUS1_ ACS_ CONFLICT_ CNT - L2_DBUS1_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus1 Conflict-Access Counter register
- L2_
DBUS1_ ACS_ HIT_ CNT - L2_DBUS1_ACS_HIT_CNT (r) register accessor: L2-Cache bus1 Hit-Access Counter register
- L2_
DBUS1_ ACS_ MISS_ CNT - L2_DBUS1_ACS_MISS_CNT (r) register accessor: L2-Cache bus1 Miss-Access Counter register
- L2_
DBUS1_ ACS_ NXTLVL_ RD_ CNT - L2_DBUS1_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus1 Next-Level-Access Counter register
- L2_
DBUS1_ ACS_ NXTLVL_ WR_ CNT - L2_DBUS1_ACS_NXTLVL_WR_CNT (r) register accessor: L2-Cache bus1 WB-Access Counter register
- L2_
DBUS2_ ACS_ CONFLICT_ CNT - L2_DBUS2_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus2 Conflict-Access Counter register
- L2_
DBUS2_ ACS_ HIT_ CNT - L2_DBUS2_ACS_HIT_CNT (r) register accessor: L2-Cache bus2 Hit-Access Counter register
- L2_
DBUS2_ ACS_ MISS_ CNT - L2_DBUS2_ACS_MISS_CNT (r) register accessor: L2-Cache bus2 Miss-Access Counter register
- L2_
DBUS2_ ACS_ NXTLVL_ RD_ CNT - L2_DBUS2_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus2 Next-Level-Access Counter register
- L2_
DBUS2_ ACS_ NXTLVL_ WR_ CNT - L2_DBUS2_ACS_NXTLVL_WR_CNT (r) register accessor: L2-Cache bus2 WB-Access Counter register
- L2_
DBUS3_ ACS_ CONFLICT_ CNT - L2_DBUS3_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus3 Conflict-Access Counter register
- L2_
DBUS3_ ACS_ HIT_ CNT - L2_DBUS3_ACS_HIT_CNT (r) register accessor: L2-Cache bus3 Hit-Access Counter register
- L2_
DBUS3_ ACS_ MISS_ CNT - L2_DBUS3_ACS_MISS_CNT (r) register accessor: L2-Cache bus3 Miss-Access Counter register
- L2_
DBUS3_ ACS_ NXTLVL_ RD_ CNT - L2_DBUS3_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus3 Next-Level-Access Counter register
- L2_
DBUS3_ ACS_ NXTLVL_ WR_ CNT - L2_DBUS3_ACS_NXTLVL_WR_CNT (r) register accessor: L2-Cache bus3 WB-Access Counter register
- L2_
IBUS0_ ACS_ CONFLICT_ CNT - L2_IBUS0_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus0 Conflict-Access Counter register
- L2_
IBUS0_ ACS_ HIT_ CNT - L2_IBUS0_ACS_HIT_CNT (r) register accessor: L2-Cache bus0 Hit-Access Counter register
- L2_
IBUS0_ ACS_ MISS_ CNT - L2_IBUS0_ACS_MISS_CNT (r) register accessor: L2-Cache bus0 Miss-Access Counter register
- L2_
IBUS0_ ACS_ NXTLVL_ RD_ CNT - L2_IBUS0_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus0 Next-Level-Access Counter register
- L2_
IBUS1_ ACS_ CONFLICT_ CNT - L2_IBUS1_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus1 Conflict-Access Counter register
- L2_
IBUS1_ ACS_ HIT_ CNT - L2_IBUS1_ACS_HIT_CNT (r) register accessor: L2-Cache bus1 Hit-Access Counter register
- L2_
IBUS1_ ACS_ MISS_ CNT - L2_IBUS1_ACS_MISS_CNT (r) register accessor: L2-Cache bus1 Miss-Access Counter register
- L2_
IBUS1_ ACS_ NXTLVL_ RD_ CNT - L2_IBUS1_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus1 Next-Level-Access Counter register
- L2_
IBUS2_ ACS_ CONFLICT_ CNT - L2_IBUS2_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus2 Conflict-Access Counter register
- L2_
IBUS2_ ACS_ HIT_ CNT - L2_IBUS2_ACS_HIT_CNT (r) register accessor: L2-Cache bus2 Hit-Access Counter register
- L2_
IBUS2_ ACS_ MISS_ CNT - L2_IBUS2_ACS_MISS_CNT (r) register accessor: L2-Cache bus2 Miss-Access Counter register
- L2_
IBUS2_ ACS_ NXTLVL_ RD_ CNT - L2_IBUS2_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus2 Next-Level-Access Counter register
- L2_
IBUS3_ ACS_ CONFLICT_ CNT - L2_IBUS3_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus3 Conflict-Access Counter register
- L2_
IBUS3_ ACS_ HIT_ CNT - L2_IBUS3_ACS_HIT_CNT (r) register accessor: L2-Cache bus3 Hit-Access Counter register
- L2_
IBUS3_ ACS_ MISS_ CNT - L2_IBUS3_ACS_MISS_CNT (r) register accessor: L2-Cache bus3 Miss-Access Counter register
- L2_
IBUS3_ ACS_ NXTLVL_ RD_ CNT - L2_IBUS3_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus3 Next-Level-Access Counter register
- L2_
UNALLOCATE_ BUFFER_ CLEAR - L2_UNALLOCATE_BUFFER_CLEAR (rw) register accessor: Unallocate request buffer clear registers
- LEVEL_
SPLI T0 - LEVEL_SPLIT0 (r) register accessor: USED TO SPLIT L1 CACHE AND L2 CACHE
- LEVEL_
SPLI T1 - LEVEL_SPLIT1 (r) register accessor: USED TO SPLIT L1 CACHE AND L2 CACHE
- LOCK_
ADDR - LOCK_ADDR (rw) register accessor: Lock (manual lock) address configure register
- LOCK_
CTRL - LOCK_CTRL (rw) register accessor: Lock-class (manual lock) operation control register
- LOCK_
MAP - LOCK_MAP (rw) register accessor: Lock (manual lock) map configure register
- LOCK_
SIZE - LOCK_SIZE (rw) register accessor: Lock (manual lock) size configure register
- REDUNDANCY_
SIG0 - REDUNDANCY_SIG0 (rw) register accessor: Cache redundancy signal 0 register
- REDUNDANCY_
SIG1 - REDUNDANCY_SIG1 (rw) register accessor: Cache redundancy signal 1 register
- REDUNDANCY_
SIG2 - REDUNDANCY_SIG2 (rw) register accessor: Cache redundancy signal 2 register
- REDUNDANCY_
SIG3 - REDUNDANCY_SIG3 (rw) register accessor: Cache redundancy signal 3 register
- REDUNDANCY_
SIG4 - REDUNDANCY_SIG4 (r) register accessor: Cache redundancy signal 0 register
- SYNC_
ADDR - SYNC_ADDR (rw) register accessor: Sync address configure register
- SYNC_
CTRL - SYNC_CTRL (rw) register accessor: Sync-class operation control register
- SYNC_
L1_ CACHE_ PRELOAD_ EXCEPTION - SYNC_L1_CACHE_PRELOAD_EXCEPTION (r) register accessor: Cache Sync/Preload Operation exception register
- SYNC_
L1_ CACHE_ PRELOAD_ INT_ CLR - SYNC_L1_CACHE_PRELOAD_INT_CLR (rw) register accessor: Sync Preload operation Interrupt clear register
- SYNC_
L1_ CACHE_ PRELOAD_ INT_ ENA - SYNC_L1_CACHE_PRELOAD_INT_ENA (rw) register accessor: L1-Cache Access Fail Interrupt enable register
- SYNC_
L1_ CACHE_ PRELOAD_ INT_ RAW - SYNC_L1_CACHE_PRELOAD_INT_RAW (rw) register accessor: Sync Preload operation Interrupt raw register
- SYNC_
L1_ CACHE_ PRELOAD_ INT_ ST - SYNC_L1_CACHE_PRELOAD_INT_ST (r) register accessor: L1-Cache Access Fail Interrupt status register
- SYNC_
MAP - SYNC_MAP (rw) register accessor: Sync map configure register
- SYNC_
SIZE - SYNC_SIZE (rw) register accessor: Sync size configure register