esp32p4/usb_device/
ser_afifo_config.rs

1#[doc = "Register `SER_AFIFO_CONFIG` reader"]
2pub type R = crate::R<SER_AFIFO_CONFIG_SPEC>;
3#[doc = "Register `SER_AFIFO_CONFIG` writer"]
4pub type W = crate::W<SER_AFIFO_CONFIG_SPEC>;
5#[doc = "Field `SERIAL_IN_AFIFO_RESET_WR` reader - Write 1 to reset CDC_ACM IN async FIFO write clock domain."]
6pub type SERIAL_IN_AFIFO_RESET_WR_R = crate::BitReader;
7#[doc = "Field `SERIAL_IN_AFIFO_RESET_WR` writer - Write 1 to reset CDC_ACM IN async FIFO write clock domain."]
8pub type SERIAL_IN_AFIFO_RESET_WR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SERIAL_IN_AFIFO_RESET_RD` reader - Write 1 to reset CDC_ACM IN async FIFO read clock domain."]
10pub type SERIAL_IN_AFIFO_RESET_RD_R = crate::BitReader;
11#[doc = "Field `SERIAL_IN_AFIFO_RESET_RD` writer - Write 1 to reset CDC_ACM IN async FIFO read clock domain."]
12pub type SERIAL_IN_AFIFO_RESET_RD_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SERIAL_OUT_AFIFO_RESET_WR` reader - Write 1 to reset CDC_ACM OUT async FIFO write clock domain."]
14pub type SERIAL_OUT_AFIFO_RESET_WR_R = crate::BitReader;
15#[doc = "Field `SERIAL_OUT_AFIFO_RESET_WR` writer - Write 1 to reset CDC_ACM OUT async FIFO write clock domain."]
16pub type SERIAL_OUT_AFIFO_RESET_WR_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SERIAL_OUT_AFIFO_RESET_RD` reader - Write 1 to reset CDC_ACM OUT async FIFO read clock domain."]
18pub type SERIAL_OUT_AFIFO_RESET_RD_R = crate::BitReader;
19#[doc = "Field `SERIAL_OUT_AFIFO_RESET_RD` writer - Write 1 to reset CDC_ACM OUT async FIFO read clock domain."]
20pub type SERIAL_OUT_AFIFO_RESET_RD_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `SERIAL_OUT_AFIFO_REMPTY` reader - CDC_ACM OUTOUT async FIFO empty signal in read clock domain."]
22pub type SERIAL_OUT_AFIFO_REMPTY_R = crate::BitReader;
23#[doc = "Field `SERIAL_IN_AFIFO_WFULL` reader - CDC_ACM OUT IN async FIFO empty signal in write clock domain."]
24pub type SERIAL_IN_AFIFO_WFULL_R = crate::BitReader;
25impl R {
26    #[doc = "Bit 0 - Write 1 to reset CDC_ACM IN async FIFO write clock domain."]
27    #[inline(always)]
28    pub fn serial_in_afifo_reset_wr(&self) -> SERIAL_IN_AFIFO_RESET_WR_R {
29        SERIAL_IN_AFIFO_RESET_WR_R::new((self.bits & 1) != 0)
30    }
31    #[doc = "Bit 1 - Write 1 to reset CDC_ACM IN async FIFO read clock domain."]
32    #[inline(always)]
33    pub fn serial_in_afifo_reset_rd(&self) -> SERIAL_IN_AFIFO_RESET_RD_R {
34        SERIAL_IN_AFIFO_RESET_RD_R::new(((self.bits >> 1) & 1) != 0)
35    }
36    #[doc = "Bit 2 - Write 1 to reset CDC_ACM OUT async FIFO write clock domain."]
37    #[inline(always)]
38    pub fn serial_out_afifo_reset_wr(&self) -> SERIAL_OUT_AFIFO_RESET_WR_R {
39        SERIAL_OUT_AFIFO_RESET_WR_R::new(((self.bits >> 2) & 1) != 0)
40    }
41    #[doc = "Bit 3 - Write 1 to reset CDC_ACM OUT async FIFO read clock domain."]
42    #[inline(always)]
43    pub fn serial_out_afifo_reset_rd(&self) -> SERIAL_OUT_AFIFO_RESET_RD_R {
44        SERIAL_OUT_AFIFO_RESET_RD_R::new(((self.bits >> 3) & 1) != 0)
45    }
46    #[doc = "Bit 4 - CDC_ACM OUTOUT async FIFO empty signal in read clock domain."]
47    #[inline(always)]
48    pub fn serial_out_afifo_rempty(&self) -> SERIAL_OUT_AFIFO_REMPTY_R {
49        SERIAL_OUT_AFIFO_REMPTY_R::new(((self.bits >> 4) & 1) != 0)
50    }
51    #[doc = "Bit 5 - CDC_ACM OUT IN async FIFO empty signal in write clock domain."]
52    #[inline(always)]
53    pub fn serial_in_afifo_wfull(&self) -> SERIAL_IN_AFIFO_WFULL_R {
54        SERIAL_IN_AFIFO_WFULL_R::new(((self.bits >> 5) & 1) != 0)
55    }
56}
57#[cfg(feature = "impl-register-debug")]
58impl core::fmt::Debug for R {
59    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
60        f.debug_struct("SER_AFIFO_CONFIG")
61            .field(
62                "serial_in_afifo_reset_wr",
63                &format_args!("{}", self.serial_in_afifo_reset_wr().bit()),
64            )
65            .field(
66                "serial_in_afifo_reset_rd",
67                &format_args!("{}", self.serial_in_afifo_reset_rd().bit()),
68            )
69            .field(
70                "serial_out_afifo_reset_wr",
71                &format_args!("{}", self.serial_out_afifo_reset_wr().bit()),
72            )
73            .field(
74                "serial_out_afifo_reset_rd",
75                &format_args!("{}", self.serial_out_afifo_reset_rd().bit()),
76            )
77            .field(
78                "serial_out_afifo_rempty",
79                &format_args!("{}", self.serial_out_afifo_rempty().bit()),
80            )
81            .field(
82                "serial_in_afifo_wfull",
83                &format_args!("{}", self.serial_in_afifo_wfull().bit()),
84            )
85            .finish()
86    }
87}
88#[cfg(feature = "impl-register-debug")]
89impl core::fmt::Debug for crate::generic::Reg<SER_AFIFO_CONFIG_SPEC> {
90    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
91        core::fmt::Debug::fmt(&self.read(), f)
92    }
93}
94impl W {
95    #[doc = "Bit 0 - Write 1 to reset CDC_ACM IN async FIFO write clock domain."]
96    #[inline(always)]
97    #[must_use]
98    pub fn serial_in_afifo_reset_wr(
99        &mut self,
100    ) -> SERIAL_IN_AFIFO_RESET_WR_W<SER_AFIFO_CONFIG_SPEC> {
101        SERIAL_IN_AFIFO_RESET_WR_W::new(self, 0)
102    }
103    #[doc = "Bit 1 - Write 1 to reset CDC_ACM IN async FIFO read clock domain."]
104    #[inline(always)]
105    #[must_use]
106    pub fn serial_in_afifo_reset_rd(
107        &mut self,
108    ) -> SERIAL_IN_AFIFO_RESET_RD_W<SER_AFIFO_CONFIG_SPEC> {
109        SERIAL_IN_AFIFO_RESET_RD_W::new(self, 1)
110    }
111    #[doc = "Bit 2 - Write 1 to reset CDC_ACM OUT async FIFO write clock domain."]
112    #[inline(always)]
113    #[must_use]
114    pub fn serial_out_afifo_reset_wr(
115        &mut self,
116    ) -> SERIAL_OUT_AFIFO_RESET_WR_W<SER_AFIFO_CONFIG_SPEC> {
117        SERIAL_OUT_AFIFO_RESET_WR_W::new(self, 2)
118    }
119    #[doc = "Bit 3 - Write 1 to reset CDC_ACM OUT async FIFO read clock domain."]
120    #[inline(always)]
121    #[must_use]
122    pub fn serial_out_afifo_reset_rd(
123        &mut self,
124    ) -> SERIAL_OUT_AFIFO_RESET_RD_W<SER_AFIFO_CONFIG_SPEC> {
125        SERIAL_OUT_AFIFO_RESET_RD_W::new(self, 3)
126    }
127}
128#[doc = "Serial AFIFO configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ser_afifo_config::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ser_afifo_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
129pub struct SER_AFIFO_CONFIG_SPEC;
130impl crate::RegisterSpec for SER_AFIFO_CONFIG_SPEC {
131    type Ux = u32;
132}
133#[doc = "`read()` method returns [`ser_afifo_config::R`](R) reader structure"]
134impl crate::Readable for SER_AFIFO_CONFIG_SPEC {}
135#[doc = "`write(|w| ..)` method takes [`ser_afifo_config::W`](W) writer structure"]
136impl crate::Writable for SER_AFIFO_CONFIG_SPEC {
137    type Safety = crate::Unsafe;
138    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
139    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
140}
141#[doc = "`reset()` method sets SER_AFIFO_CONFIG to value 0x10"]
142impl crate::Resettable for SER_AFIFO_CONFIG_SPEC {
143    const RESET_VALUE: u32 = 0x10;
144}
esp32p4/usb_device/ser_afifo_config.rs

esp32p4/usb_device/
ser_afifo_config.rs
