1#[doc = "Register `EVT_ST5_CLR` writer"]
2pub type W = crate::W<EVT_ST5_CLR_SPEC>;
3#[doc = "Field `ULP_EVT_ERR_INTR_ST_CLR` writer - Configures whether or not to clear ULP_evt_err_intr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
4pub type ULP_EVT_ERR_INTR_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `ULP_EVT_HALT_ST_CLR` writer - Configures whether or not to clear ULP_evt_halt trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
6pub type ULP_EVT_HALT_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `ULP_EVT_START_INTR_ST_CLR` writer - Configures whether or not to clear ULP_evt_start_intr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
8pub type ULP_EVT_START_INTR_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `RTC_EVT_TICK_ST_CLR` writer - Configures whether or not to clear RTC_evt_tick trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
10pub type RTC_EVT_TICK_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `RTC_EVT_OVF_ST_CLR` writer - Configures whether or not to clear RTC_evt_ovf trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
12pub type RTC_EVT_OVF_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RTC_EVT_CMP_ST_CLR` writer - Configures whether or not to clear RTC_evt_cmp trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
14pub type RTC_EVT_CMP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
16pub type PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
18pub type PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_done_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
20pub type PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
22pub type PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
24pub type PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
26pub type PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
28pub type PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
30pub type PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
32pub type PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
34pub type PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
36pub type PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
38pub type PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
39#[doc = "Field `PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
40pub type PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
42pub type PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
43#[doc = "Field `PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_done_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
44pub type PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
46pub type PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
47#[doc = "Field `PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
48pub type PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
50pub type PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
51#[doc = "Field `PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
52pub type PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
54pub type PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
55#[doc = "Field `PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
56pub type PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
58pub type PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
59#[doc = "Field `PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
60pub type PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
62pub type PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
63#[doc = "Field `PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
64pub type PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
66pub type PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
67#[cfg(feature = "impl-register-debug")]
68impl core::fmt::Debug for crate::generic::Reg<EVT_ST5_CLR_SPEC> {
69 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
70 write!(f, "(not readable)")
71 }
72}
73impl W {
74 #[doc = "Bit 0 - Configures whether or not to clear ULP_evt_err_intr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
75 #[inline(always)]
76 #[must_use]
77 pub fn ulp_evt_err_intr_st_clr(&mut self) -> ULP_EVT_ERR_INTR_ST_CLR_W<EVT_ST5_CLR_SPEC> {
78 ULP_EVT_ERR_INTR_ST_CLR_W::new(self, 0)
79 }
80 #[doc = "Bit 1 - Configures whether or not to clear ULP_evt_halt trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
81 #[inline(always)]
82 #[must_use]
83 pub fn ulp_evt_halt_st_clr(&mut self) -> ULP_EVT_HALT_ST_CLR_W<EVT_ST5_CLR_SPEC> {
84 ULP_EVT_HALT_ST_CLR_W::new(self, 1)
85 }
86 #[doc = "Bit 2 - Configures whether or not to clear ULP_evt_start_intr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
87 #[inline(always)]
88 #[must_use]
89 pub fn ulp_evt_start_intr_st_clr(&mut self) -> ULP_EVT_START_INTR_ST_CLR_W<EVT_ST5_CLR_SPEC> {
90 ULP_EVT_START_INTR_ST_CLR_W::new(self, 2)
91 }
92 #[doc = "Bit 3 - Configures whether or not to clear RTC_evt_tick trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
93 #[inline(always)]
94 #[must_use]
95 pub fn rtc_evt_tick_st_clr(&mut self) -> RTC_EVT_TICK_ST_CLR_W<EVT_ST5_CLR_SPEC> {
96 RTC_EVT_TICK_ST_CLR_W::new(self, 3)
97 }
98 #[doc = "Bit 4 - Configures whether or not to clear RTC_evt_ovf trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
99 #[inline(always)]
100 #[must_use]
101 pub fn rtc_evt_ovf_st_clr(&mut self) -> RTC_EVT_OVF_ST_CLR_W<EVT_ST5_CLR_SPEC> {
102 RTC_EVT_OVF_ST_CLR_W::new(self, 4)
103 }
104 #[doc = "Bit 5 - Configures whether or not to clear RTC_evt_cmp trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
105 #[inline(always)]
106 #[must_use]
107 pub fn rtc_evt_cmp_st_clr(&mut self) -> RTC_EVT_CMP_ST_CLR_W<EVT_ST5_CLR_SPEC> {
108 RTC_EVT_CMP_ST_CLR_W::new(self, 5)
109 }
110 #[doc = "Bit 6 - Configures whether or not to clear PDMA_AHB_evt_in_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
111 #[inline(always)]
112 #[must_use]
113 pub fn pdma_ahb_evt_in_done_ch0_st_clr(
114 &mut self,
115 ) -> PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_W<EVT_ST5_CLR_SPEC> {
116 PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_W::new(self, 6)
117 }
118 #[doc = "Bit 7 - Configures whether or not to clear PDMA_AHB_evt_in_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
119 #[inline(always)]
120 #[must_use]
121 pub fn pdma_ahb_evt_in_done_ch1_st_clr(
122 &mut self,
123 ) -> PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_W<EVT_ST5_CLR_SPEC> {
124 PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_W::new(self, 7)
125 }
126 #[doc = "Bit 8 - Configures whether or not to clear PDMA_AHB_evt_in_done_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
127 #[inline(always)]
128 #[must_use]
129 pub fn pdma_ahb_evt_in_done_ch2_st_clr(
130 &mut self,
131 ) -> PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_W<EVT_ST5_CLR_SPEC> {
132 PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_W::new(self, 8)
133 }
134 #[doc = "Bit 9 - Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
135 #[inline(always)]
136 #[must_use]
137 pub fn pdma_ahb_evt_in_suc_eof_ch0_st_clr(
138 &mut self,
139 ) -> PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_W<EVT_ST5_CLR_SPEC> {
140 PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_W::new(self, 9)
141 }
142 #[doc = "Bit 10 - Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
143 #[inline(always)]
144 #[must_use]
145 pub fn pdma_ahb_evt_in_suc_eof_ch1_st_clr(
146 &mut self,
147 ) -> PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_W<EVT_ST5_CLR_SPEC> {
148 PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_W::new(self, 10)
149 }
150 #[doc = "Bit 11 - Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
151 #[inline(always)]
152 #[must_use]
153 pub fn pdma_ahb_evt_in_suc_eof_ch2_st_clr(
154 &mut self,
155 ) -> PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_W<EVT_ST5_CLR_SPEC> {
156 PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_W::new(self, 11)
157 }
158 #[doc = "Bit 12 - Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
159 #[inline(always)]
160 #[must_use]
161 pub fn pdma_ahb_evt_in_fifo_empty_ch0_st_clr(
162 &mut self,
163 ) -> PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_W<EVT_ST5_CLR_SPEC> {
164 PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_W::new(self, 12)
165 }
166 #[doc = "Bit 13 - Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
167 #[inline(always)]
168 #[must_use]
169 pub fn pdma_ahb_evt_in_fifo_empty_ch1_st_clr(
170 &mut self,
171 ) -> PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_W<EVT_ST5_CLR_SPEC> {
172 PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_W::new(self, 13)
173 }
174 #[doc = "Bit 14 - Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
175 #[inline(always)]
176 #[must_use]
177 pub fn pdma_ahb_evt_in_fifo_empty_ch2_st_clr(
178 &mut self,
179 ) -> PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_W<EVT_ST5_CLR_SPEC> {
180 PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_W::new(self, 14)
181 }
182 #[doc = "Bit 15 - Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
183 #[inline(always)]
184 #[must_use]
185 pub fn pdma_ahb_evt_in_fifo_full_ch0_st_clr(
186 &mut self,
187 ) -> PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_W<EVT_ST5_CLR_SPEC> {
188 PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_W::new(self, 15)
189 }
190 #[doc = "Bit 16 - Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
191 #[inline(always)]
192 #[must_use]
193 pub fn pdma_ahb_evt_in_fifo_full_ch1_st_clr(
194 &mut self,
195 ) -> PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_W<EVT_ST5_CLR_SPEC> {
196 PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_W::new(self, 16)
197 }
198 #[doc = "Bit 17 - Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
199 #[inline(always)]
200 #[must_use]
201 pub fn pdma_ahb_evt_in_fifo_full_ch2_st_clr(
202 &mut self,
203 ) -> PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_W<EVT_ST5_CLR_SPEC> {
204 PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_W::new(self, 17)
205 }
206 #[doc = "Bit 18 - Configures whether or not to clear PDMA_AHB_evt_out_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
207 #[inline(always)]
208 #[must_use]
209 pub fn pdma_ahb_evt_out_done_ch0_st_clr(
210 &mut self,
211 ) -> PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_W<EVT_ST5_CLR_SPEC> {
212 PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_W::new(self, 18)
213 }
214 #[doc = "Bit 19 - Configures whether or not to clear PDMA_AHB_evt_out_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
215 #[inline(always)]
216 #[must_use]
217 pub fn pdma_ahb_evt_out_done_ch1_st_clr(
218 &mut self,
219 ) -> PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_W<EVT_ST5_CLR_SPEC> {
220 PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_W::new(self, 19)
221 }
222 #[doc = "Bit 20 - Configures whether or not to clear PDMA_AHB_evt_out_done_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
223 #[inline(always)]
224 #[must_use]
225 pub fn pdma_ahb_evt_out_done_ch2_st_clr(
226 &mut self,
227 ) -> PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_W<EVT_ST5_CLR_SPEC> {
228 PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_W::new(self, 20)
229 }
230 #[doc = "Bit 21 - Configures whether or not to clear PDMA_AHB_evt_out_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
231 #[inline(always)]
232 #[must_use]
233 pub fn pdma_ahb_evt_out_eof_ch0_st_clr(
234 &mut self,
235 ) -> PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_W<EVT_ST5_CLR_SPEC> {
236 PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_W::new(self, 21)
237 }
238 #[doc = "Bit 22 - Configures whether or not to clear PDMA_AHB_evt_out_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
239 #[inline(always)]
240 #[must_use]
241 pub fn pdma_ahb_evt_out_eof_ch1_st_clr(
242 &mut self,
243 ) -> PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_W<EVT_ST5_CLR_SPEC> {
244 PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_W::new(self, 22)
245 }
246 #[doc = "Bit 23 - Configures whether or not to clear PDMA_AHB_evt_out_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
247 #[inline(always)]
248 #[must_use]
249 pub fn pdma_ahb_evt_out_eof_ch2_st_clr(
250 &mut self,
251 ) -> PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_W<EVT_ST5_CLR_SPEC> {
252 PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_W::new(self, 23)
253 }
254 #[doc = "Bit 24 - Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
255 #[inline(always)]
256 #[must_use]
257 pub fn pdma_ahb_evt_out_total_eof_ch0_st_clr(
258 &mut self,
259 ) -> PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_W<EVT_ST5_CLR_SPEC> {
260 PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_W::new(self, 24)
261 }
262 #[doc = "Bit 25 - Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
263 #[inline(always)]
264 #[must_use]
265 pub fn pdma_ahb_evt_out_total_eof_ch1_st_clr(
266 &mut self,
267 ) -> PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_W<EVT_ST5_CLR_SPEC> {
268 PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_W::new(self, 25)
269 }
270 #[doc = "Bit 26 - Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
271 #[inline(always)]
272 #[must_use]
273 pub fn pdma_ahb_evt_out_total_eof_ch2_st_clr(
274 &mut self,
275 ) -> PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_W<EVT_ST5_CLR_SPEC> {
276 PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_W::new(self, 26)
277 }
278 #[doc = "Bit 27 - Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
279 #[inline(always)]
280 #[must_use]
281 pub fn pdma_ahb_evt_out_fifo_empty_ch0_st_clr(
282 &mut self,
283 ) -> PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_W<EVT_ST5_CLR_SPEC> {
284 PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_W::new(self, 27)
285 }
286 #[doc = "Bit 28 - Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
287 #[inline(always)]
288 #[must_use]
289 pub fn pdma_ahb_evt_out_fifo_empty_ch1_st_clr(
290 &mut self,
291 ) -> PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_W<EVT_ST5_CLR_SPEC> {
292 PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_W::new(self, 28)
293 }
294 #[doc = "Bit 29 - Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
295 #[inline(always)]
296 #[must_use]
297 pub fn pdma_ahb_evt_out_fifo_empty_ch2_st_clr(
298 &mut self,
299 ) -> PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_W<EVT_ST5_CLR_SPEC> {
300 PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_W::new(self, 29)
301 }
302 #[doc = "Bit 30 - Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
303 #[inline(always)]
304 #[must_use]
305 pub fn pdma_ahb_evt_out_fifo_full_ch0_st_clr(
306 &mut self,
307 ) -> PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_W<EVT_ST5_CLR_SPEC> {
308 PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_W::new(self, 30)
309 }
310 #[doc = "Bit 31 - Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
311 #[inline(always)]
312 #[must_use]
313 pub fn pdma_ahb_evt_out_fifo_full_ch1_st_clr(
314 &mut self,
315 ) -> PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_W<EVT_ST5_CLR_SPEC> {
316 PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_W::new(self, 31)
317 }
318}
319#[doc = "Events trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st5_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
320pub struct EVT_ST5_CLR_SPEC;
321impl crate::RegisterSpec for EVT_ST5_CLR_SPEC {
322 type Ux = u32;
323}
324#[doc = "`write(|w| ..)` method takes [`evt_st5_clr::W`](W) writer structure"]
325impl crate::Writable for EVT_ST5_CLR_SPEC {
326 type Safety = crate::Unsafe;
327 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
328 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
329}
330#[doc = "`reset()` method sets EVT_ST5_CLR to value 0"]
331impl crate::Resettable for EVT_ST5_CLR_SPEC {
332 const RESET_VALUE: u32 = 0;
333}