esp32p4/parl_io/
tx_clk_cfg.rs

1#[doc = "Register `TX_CLK_CFG` reader"]
2pub type R = crate::R<TX_CLK_CFG_SPEC>;
3#[doc = "Register `TX_CLK_CFG` writer"]
4pub type W = crate::W<TX_CLK_CFG_SPEC>;
5#[doc = "Field `TX_CLK_I_INV` reader - Set this bit to invert the input Tx core clock."]
6pub type TX_CLK_I_INV_R = crate::BitReader;
7#[doc = "Field `TX_CLK_I_INV` writer - Set this bit to invert the input Tx core clock."]
8pub type TX_CLK_I_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TX_CLK_O_INV` reader - Set this bit to invert the output Tx core clock."]
10pub type TX_CLK_O_INV_R = crate::BitReader;
11#[doc = "Field `TX_CLK_O_INV` writer - Set this bit to invert the output Tx core clock."]
12pub type TX_CLK_O_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    #[doc = "Bit 30 - Set this bit to invert the input Tx core clock."]
15    #[inline(always)]
16    pub fn tx_clk_i_inv(&self) -> TX_CLK_I_INV_R {
17        TX_CLK_I_INV_R::new(((self.bits >> 30) & 1) != 0)
18    }
19    #[doc = "Bit 31 - Set this bit to invert the output Tx core clock."]
20    #[inline(always)]
21    pub fn tx_clk_o_inv(&self) -> TX_CLK_O_INV_R {
22        TX_CLK_O_INV_R::new(((self.bits >> 31) & 1) != 0)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("TX_CLK_CFG")
29            .field(
30                "tx_clk_i_inv",
31                &format_args!("{}", self.tx_clk_i_inv().bit()),
32            )
33            .field(
34                "tx_clk_o_inv",
35                &format_args!("{}", self.tx_clk_o_inv().bit()),
36            )
37            .finish()
38    }
39}
40#[cfg(feature = "impl-register-debug")]
41impl core::fmt::Debug for crate::generic::Reg<TX_CLK_CFG_SPEC> {
42    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
43        core::fmt::Debug::fmt(&self.read(), f)
44    }
45}
46impl W {
47    #[doc = "Bit 30 - Set this bit to invert the input Tx core clock."]
48    #[inline(always)]
49    #[must_use]
50    pub fn tx_clk_i_inv(&mut self) -> TX_CLK_I_INV_W<TX_CLK_CFG_SPEC> {
51        TX_CLK_I_INV_W::new(self, 30)
52    }
53    #[doc = "Bit 31 - Set this bit to invert the output Tx core clock."]
54    #[inline(always)]
55    #[must_use]
56    pub fn tx_clk_o_inv(&mut self) -> TX_CLK_O_INV_W<TX_CLK_CFG_SPEC> {
57        TX_CLK_O_INV_W::new(self, 31)
58    }
59}
60#[doc = "Parallel IO TX clk configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_clk_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_clk_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
61pub struct TX_CLK_CFG_SPEC;
62impl crate::RegisterSpec for TX_CLK_CFG_SPEC {
63    type Ux = u32;
64}
65#[doc = "`read()` method returns [`tx_clk_cfg::R`](R) reader structure"]
66impl crate::Readable for TX_CLK_CFG_SPEC {}
67#[doc = "`write(|w| ..)` method takes [`tx_clk_cfg::W`](W) writer structure"]
68impl crate::Writable for TX_CLK_CFG_SPEC {
69    type Safety = crate::Unsafe;
70    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
71    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
72}
73#[doc = "`reset()` method sets TX_CLK_CFG to value 0"]
74impl crate::Resettable for TX_CLK_CFG_SPEC {
75    const RESET_VALUE: u32 = 0;
76}
esp32p4/parl_io/tx_clk_cfg.rs

esp32p4/parl_io/
tx_clk_cfg.rs
