1#[doc = "Register `INT_RAW` reader"]
2pub type R = crate::R<INT_RAW_SPEC>;
3#[doc = "Register `INT_RAW` writer"]
4pub type W = crate::W<INT_RAW_SPEC>;
5#[doc = "Field `TIMER0_STOP` reader - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 0 stops."]
6pub type TIMER0_STOP_R = crate::BitReader;
7#[doc = "Field `TIMER0_STOP` writer - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 0 stops."]
8pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TIMER1_STOP` reader - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 1 stops."]
10pub type TIMER1_STOP_R = crate::BitReader;
11#[doc = "Field `TIMER1_STOP` writer - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 1 stops."]
12pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `TIMER2_STOP` reader - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 2 stops."]
14pub type TIMER2_STOP_R = crate::BitReader;
15#[doc = "Field `TIMER2_STOP` writer - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 2 stops."]
16pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `TIMER0_TEZ` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEZ event."]
18pub type TIMER0_TEZ_R = crate::BitReader;
19#[doc = "Field `TIMER0_TEZ` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEZ event."]
20pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TIMER1_TEZ` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEZ event."]
22pub type TIMER1_TEZ_R = crate::BitReader;
23#[doc = "Field `TIMER1_TEZ` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEZ event."]
24pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `TIMER2_TEZ` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEZ event."]
26pub type TIMER2_TEZ_R = crate::BitReader;
27#[doc = "Field `TIMER2_TEZ` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEZ event."]
28pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `TIMER0_TEP` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEP event."]
30pub type TIMER0_TEP_R = crate::BitReader;
31#[doc = "Field `TIMER0_TEP` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEP event."]
32pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `TIMER1_TEP` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEP event."]
34pub type TIMER1_TEP_R = crate::BitReader;
35#[doc = "Field `TIMER1_TEP` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEP event."]
36pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `TIMER2_TEP` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEP event."]
38pub type TIMER2_TEP_R = crate::BitReader;
39#[doc = "Field `TIMER2_TEP` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEP event."]
40pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `FAULT0` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 starts."]
42pub type FAULT0_R = crate::BitReader;
43#[doc = "Field `FAULT0` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 starts."]
44pub type FAULT0_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `FAULT1` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 starts."]
46pub type FAULT1_R = crate::BitReader;
47#[doc = "Field `FAULT1` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 starts."]
48pub type FAULT1_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `FAULT2` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 starts."]
50pub type FAULT2_R = crate::BitReader;
51#[doc = "Field `FAULT2` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 starts."]
52pub type FAULT2_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `FAULT0_CLR` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 clears."]
54pub type FAULT0_CLR_R = crate::BitReader;
55#[doc = "Field `FAULT0_CLR` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 clears."]
56pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `FAULT1_CLR` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 clears."]
58pub type FAULT1_CLR_R = crate::BitReader;
59#[doc = "Field `FAULT1_CLR` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 clears."]
60pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `FAULT2_CLR` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 clears."]
62pub type FAULT2_CLR_R = crate::BitReader;
63#[doc = "Field `FAULT2_CLR` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 clears."]
64pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `CMPR0_TEA` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEA event"]
66pub type CMPR0_TEA_R = crate::BitReader;
67#[doc = "Field `CMPR0_TEA` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEA event"]
68pub type CMPR0_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `CMPR1_TEA` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEA event"]
70pub type CMPR1_TEA_R = crate::BitReader;
71#[doc = "Field `CMPR1_TEA` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEA event"]
72pub type CMPR1_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `CMPR2_TEA` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEA event"]
74pub type CMPR2_TEA_R = crate::BitReader;
75#[doc = "Field `CMPR2_TEA` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEA event"]
76pub type CMPR2_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `CMPR0_TEB` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEB event"]
78pub type CMPR0_TEB_R = crate::BitReader;
79#[doc = "Field `CMPR0_TEB` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEB event"]
80pub type CMPR0_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `CMPR1_TEB` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEB event"]
82pub type CMPR1_TEB_R = crate::BitReader;
83#[doc = "Field `CMPR1_TEB` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEB event"]
84pub type CMPR1_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `CMPR2_TEB` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEB event"]
86pub type CMPR2_TEB_R = crate::BitReader;
87#[doc = "Field `CMPR2_TEB` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEB event"]
88pub type CMPR2_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `TZ0_CBC` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
90pub type TZ0_CBC_R = crate::BitReader;
91#[doc = "Field `TZ0_CBC` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
92pub type TZ0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
93#[doc = "Field `TZ1_CBC` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
94pub type TZ1_CBC_R = crate::BitReader;
95#[doc = "Field `TZ1_CBC` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
96pub type TZ1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
97#[doc = "Field `TZ2_CBC` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
98pub type TZ2_CBC_R = crate::BitReader;
99#[doc = "Field `TZ2_CBC` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
100pub type TZ2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
101#[doc = "Field `TZ0_OST` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM0."]
102pub type TZ0_OST_R = crate::BitReader;
103#[doc = "Field `TZ0_OST` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM0."]
104pub type TZ0_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
105#[doc = "Field `TZ1_OST` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM1."]
106pub type TZ1_OST_R = crate::BitReader;
107#[doc = "Field `TZ1_OST` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM1."]
108pub type TZ1_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
109#[doc = "Field `TZ2_OST` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM2."]
110pub type TZ2_OST_R = crate::BitReader;
111#[doc = "Field `TZ2_OST` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM2."]
112pub type TZ2_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
113#[doc = "Field `CAP0` reader - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP0."]
114pub type CAP0_R = crate::BitReader;
115#[doc = "Field `CAP0` writer - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP0."]
116pub type CAP0_W<'a, REG> = crate::BitWriter<'a, REG>;
117#[doc = "Field `CAP1` reader - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP1."]
118pub type CAP1_R = crate::BitReader;
119#[doc = "Field `CAP1` writer - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP1."]
120pub type CAP1_W<'a, REG> = crate::BitWriter<'a, REG>;
121#[doc = "Field `CAP2` reader - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP2."]
122pub type CAP2_R = crate::BitReader;
123#[doc = "Field `CAP2` writer - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP2."]
124pub type CAP2_W<'a, REG> = crate::BitWriter<'a, REG>;
125impl R {
126 #[doc = "Bit 0 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 0 stops."]
127 #[inline(always)]
128 pub fn timer0_stop(&self) -> TIMER0_STOP_R {
129 TIMER0_STOP_R::new((self.bits & 1) != 0)
130 }
131 #[doc = "Bit 1 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 1 stops."]
132 #[inline(always)]
133 pub fn timer1_stop(&self) -> TIMER1_STOP_R {
134 TIMER1_STOP_R::new(((self.bits >> 1) & 1) != 0)
135 }
136 #[doc = "Bit 2 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 2 stops."]
137 #[inline(always)]
138 pub fn timer2_stop(&self) -> TIMER2_STOP_R {
139 TIMER2_STOP_R::new(((self.bits >> 2) & 1) != 0)
140 }
141 #[doc = "Bit 3 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEZ event."]
142 #[inline(always)]
143 pub fn timer0_tez(&self) -> TIMER0_TEZ_R {
144 TIMER0_TEZ_R::new(((self.bits >> 3) & 1) != 0)
145 }
146 #[doc = "Bit 4 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEZ event."]
147 #[inline(always)]
148 pub fn timer1_tez(&self) -> TIMER1_TEZ_R {
149 TIMER1_TEZ_R::new(((self.bits >> 4) & 1) != 0)
150 }
151 #[doc = "Bit 5 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEZ event."]
152 #[inline(always)]
153 pub fn timer2_tez(&self) -> TIMER2_TEZ_R {
154 TIMER2_TEZ_R::new(((self.bits >> 5) & 1) != 0)
155 }
156 #[doc = "Bit 6 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEP event."]
157 #[inline(always)]
158 pub fn timer0_tep(&self) -> TIMER0_TEP_R {
159 TIMER0_TEP_R::new(((self.bits >> 6) & 1) != 0)
160 }
161 #[doc = "Bit 7 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEP event."]
162 #[inline(always)]
163 pub fn timer1_tep(&self) -> TIMER1_TEP_R {
164 TIMER1_TEP_R::new(((self.bits >> 7) & 1) != 0)
165 }
166 #[doc = "Bit 8 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEP event."]
167 #[inline(always)]
168 pub fn timer2_tep(&self) -> TIMER2_TEP_R {
169 TIMER2_TEP_R::new(((self.bits >> 8) & 1) != 0)
170 }
171 #[doc = "Bit 9 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 starts."]
172 #[inline(always)]
173 pub fn fault0(&self) -> FAULT0_R {
174 FAULT0_R::new(((self.bits >> 9) & 1) != 0)
175 }
176 #[doc = "Bit 10 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 starts."]
177 #[inline(always)]
178 pub fn fault1(&self) -> FAULT1_R {
179 FAULT1_R::new(((self.bits >> 10) & 1) != 0)
180 }
181 #[doc = "Bit 11 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 starts."]
182 #[inline(always)]
183 pub fn fault2(&self) -> FAULT2_R {
184 FAULT2_R::new(((self.bits >> 11) & 1) != 0)
185 }
186 #[doc = "Bit 12 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 clears."]
187 #[inline(always)]
188 pub fn fault0_clr(&self) -> FAULT0_CLR_R {
189 FAULT0_CLR_R::new(((self.bits >> 12) & 1) != 0)
190 }
191 #[doc = "Bit 13 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 clears."]
192 #[inline(always)]
193 pub fn fault1_clr(&self) -> FAULT1_CLR_R {
194 FAULT1_CLR_R::new(((self.bits >> 13) & 1) != 0)
195 }
196 #[doc = "Bit 14 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 clears."]
197 #[inline(always)]
198 pub fn fault2_clr(&self) -> FAULT2_CLR_R {
199 FAULT2_CLR_R::new(((self.bits >> 14) & 1) != 0)
200 }
201 #[doc = "Bit 15 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEA event"]
202 #[inline(always)]
203 pub fn cmpr0_tea(&self) -> CMPR0_TEA_R {
204 CMPR0_TEA_R::new(((self.bits >> 15) & 1) != 0)
205 }
206 #[doc = "Bit 16 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEA event"]
207 #[inline(always)]
208 pub fn cmpr1_tea(&self) -> CMPR1_TEA_R {
209 CMPR1_TEA_R::new(((self.bits >> 16) & 1) != 0)
210 }
211 #[doc = "Bit 17 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEA event"]
212 #[inline(always)]
213 pub fn cmpr2_tea(&self) -> CMPR2_TEA_R {
214 CMPR2_TEA_R::new(((self.bits >> 17) & 1) != 0)
215 }
216 #[doc = "Bit 18 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEB event"]
217 #[inline(always)]
218 pub fn cmpr0_teb(&self) -> CMPR0_TEB_R {
219 CMPR0_TEB_R::new(((self.bits >> 18) & 1) != 0)
220 }
221 #[doc = "Bit 19 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEB event"]
222 #[inline(always)]
223 pub fn cmpr1_teb(&self) -> CMPR1_TEB_R {
224 CMPR1_TEB_R::new(((self.bits >> 19) & 1) != 0)
225 }
226 #[doc = "Bit 20 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEB event"]
227 #[inline(always)]
228 pub fn cmpr2_teb(&self) -> CMPR2_TEB_R {
229 CMPR2_TEB_R::new(((self.bits >> 20) & 1) != 0)
230 }
231 #[doc = "Bit 21 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
232 #[inline(always)]
233 pub fn tz0_cbc(&self) -> TZ0_CBC_R {
234 TZ0_CBC_R::new(((self.bits >> 21) & 1) != 0)
235 }
236 #[doc = "Bit 22 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
237 #[inline(always)]
238 pub fn tz1_cbc(&self) -> TZ1_CBC_R {
239 TZ1_CBC_R::new(((self.bits >> 22) & 1) != 0)
240 }
241 #[doc = "Bit 23 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
242 #[inline(always)]
243 pub fn tz2_cbc(&self) -> TZ2_CBC_R {
244 TZ2_CBC_R::new(((self.bits >> 23) & 1) != 0)
245 }
246 #[doc = "Bit 24 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM0."]
247 #[inline(always)]
248 pub fn tz0_ost(&self) -> TZ0_OST_R {
249 TZ0_OST_R::new(((self.bits >> 24) & 1) != 0)
250 }
251 #[doc = "Bit 25 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM1."]
252 #[inline(always)]
253 pub fn tz1_ost(&self) -> TZ1_OST_R {
254 TZ1_OST_R::new(((self.bits >> 25) & 1) != 0)
255 }
256 #[doc = "Bit 26 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM2."]
257 #[inline(always)]
258 pub fn tz2_ost(&self) -> TZ2_OST_R {
259 TZ2_OST_R::new(((self.bits >> 26) & 1) != 0)
260 }
261 #[doc = "Bit 27 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP0."]
262 #[inline(always)]
263 pub fn cap0(&self) -> CAP0_R {
264 CAP0_R::new(((self.bits >> 27) & 1) != 0)
265 }
266 #[doc = "Bit 28 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP1."]
267 #[inline(always)]
268 pub fn cap1(&self) -> CAP1_R {
269 CAP1_R::new(((self.bits >> 28) & 1) != 0)
270 }
271 #[doc = "Bit 29 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP2."]
272 #[inline(always)]
273 pub fn cap2(&self) -> CAP2_R {
274 CAP2_R::new(((self.bits >> 29) & 1) != 0)
275 }
276}
277#[cfg(feature = "impl-register-debug")]
278impl core::fmt::Debug for R {
279 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
280 f.debug_struct("INT_RAW")
281 .field("timer0_stop", &format_args!("{}", self.timer0_stop().bit()))
282 .field("timer1_stop", &format_args!("{}", self.timer1_stop().bit()))
283 .field("timer2_stop", &format_args!("{}", self.timer2_stop().bit()))
284 .field("timer0_tez", &format_args!("{}", self.timer0_tez().bit()))
285 .field("timer1_tez", &format_args!("{}", self.timer1_tez().bit()))
286 .field("timer2_tez", &format_args!("{}", self.timer2_tez().bit()))
287 .field("timer0_tep", &format_args!("{}", self.timer0_tep().bit()))
288 .field("timer1_tep", &format_args!("{}", self.timer1_tep().bit()))
289 .field("timer2_tep", &format_args!("{}", self.timer2_tep().bit()))
290 .field("fault0", &format_args!("{}", self.fault0().bit()))
291 .field("fault1", &format_args!("{}", self.fault1().bit()))
292 .field("fault2", &format_args!("{}", self.fault2().bit()))
293 .field("fault0_clr", &format_args!("{}", self.fault0_clr().bit()))
294 .field("fault1_clr", &format_args!("{}", self.fault1_clr().bit()))
295 .field("fault2_clr", &format_args!("{}", self.fault2_clr().bit()))
296 .field("cmpr0_tea", &format_args!("{}", self.cmpr0_tea().bit()))
297 .field("cmpr1_tea", &format_args!("{}", self.cmpr1_tea().bit()))
298 .field("cmpr2_tea", &format_args!("{}", self.cmpr2_tea().bit()))
299 .field("cmpr0_teb", &format_args!("{}", self.cmpr0_teb().bit()))
300 .field("cmpr1_teb", &format_args!("{}", self.cmpr1_teb().bit()))
301 .field("cmpr2_teb", &format_args!("{}", self.cmpr2_teb().bit()))
302 .field("tz0_cbc", &format_args!("{}", self.tz0_cbc().bit()))
303 .field("tz1_cbc", &format_args!("{}", self.tz1_cbc().bit()))
304 .field("tz2_cbc", &format_args!("{}", self.tz2_cbc().bit()))
305 .field("tz0_ost", &format_args!("{}", self.tz0_ost().bit()))
306 .field("tz1_ost", &format_args!("{}", self.tz1_ost().bit()))
307 .field("tz2_ost", &format_args!("{}", self.tz2_ost().bit()))
308 .field("cap0", &format_args!("{}", self.cap0().bit()))
309 .field("cap1", &format_args!("{}", self.cap1().bit()))
310 .field("cap2", &format_args!("{}", self.cap2().bit()))
311 .finish()
312 }
313}
314#[cfg(feature = "impl-register-debug")]
315impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
316 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
317 core::fmt::Debug::fmt(&self.read(), f)
318 }
319}
320impl W {
321 #[doc = "Bit 0 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 0 stops."]
322 #[inline(always)]
323 #[must_use]
324 pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<INT_RAW_SPEC> {
325 TIMER0_STOP_W::new(self, 0)
326 }
327 #[doc = "Bit 1 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 1 stops."]
328 #[inline(always)]
329 #[must_use]
330 pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<INT_RAW_SPEC> {
331 TIMER1_STOP_W::new(self, 1)
332 }
333 #[doc = "Bit 2 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 2 stops."]
334 #[inline(always)]
335 #[must_use]
336 pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<INT_RAW_SPEC> {
337 TIMER2_STOP_W::new(self, 2)
338 }
339 #[doc = "Bit 3 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEZ event."]
340 #[inline(always)]
341 #[must_use]
342 pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<INT_RAW_SPEC> {
343 TIMER0_TEZ_W::new(self, 3)
344 }
345 #[doc = "Bit 4 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEZ event."]
346 #[inline(always)]
347 #[must_use]
348 pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<INT_RAW_SPEC> {
349 TIMER1_TEZ_W::new(self, 4)
350 }
351 #[doc = "Bit 5 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEZ event."]
352 #[inline(always)]
353 #[must_use]
354 pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<INT_RAW_SPEC> {
355 TIMER2_TEZ_W::new(self, 5)
356 }
357 #[doc = "Bit 6 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEP event."]
358 #[inline(always)]
359 #[must_use]
360 pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<INT_RAW_SPEC> {
361 TIMER0_TEP_W::new(self, 6)
362 }
363 #[doc = "Bit 7 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEP event."]
364 #[inline(always)]
365 #[must_use]
366 pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<INT_RAW_SPEC> {
367 TIMER1_TEP_W::new(self, 7)
368 }
369 #[doc = "Bit 8 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEP event."]
370 #[inline(always)]
371 #[must_use]
372 pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<INT_RAW_SPEC> {
373 TIMER2_TEP_W::new(self, 8)
374 }
375 #[doc = "Bit 9 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 starts."]
376 #[inline(always)]
377 #[must_use]
378 pub fn fault0(&mut self) -> FAULT0_W<INT_RAW_SPEC> {
379 FAULT0_W::new(self, 9)
380 }
381 #[doc = "Bit 10 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 starts."]
382 #[inline(always)]
383 #[must_use]
384 pub fn fault1(&mut self) -> FAULT1_W<INT_RAW_SPEC> {
385 FAULT1_W::new(self, 10)
386 }
387 #[doc = "Bit 11 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 starts."]
388 #[inline(always)]
389 #[must_use]
390 pub fn fault2(&mut self) -> FAULT2_W<INT_RAW_SPEC> {
391 FAULT2_W::new(self, 11)
392 }
393 #[doc = "Bit 12 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 clears."]
394 #[inline(always)]
395 #[must_use]
396 pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<INT_RAW_SPEC> {
397 FAULT0_CLR_W::new(self, 12)
398 }
399 #[doc = "Bit 13 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 clears."]
400 #[inline(always)]
401 #[must_use]
402 pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<INT_RAW_SPEC> {
403 FAULT1_CLR_W::new(self, 13)
404 }
405 #[doc = "Bit 14 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 clears."]
406 #[inline(always)]
407 #[must_use]
408 pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<INT_RAW_SPEC> {
409 FAULT2_CLR_W::new(self, 14)
410 }
411 #[doc = "Bit 15 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEA event"]
412 #[inline(always)]
413 #[must_use]
414 pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<INT_RAW_SPEC> {
415 CMPR0_TEA_W::new(self, 15)
416 }
417 #[doc = "Bit 16 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEA event"]
418 #[inline(always)]
419 #[must_use]
420 pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<INT_RAW_SPEC> {
421 CMPR1_TEA_W::new(self, 16)
422 }
423 #[doc = "Bit 17 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEA event"]
424 #[inline(always)]
425 #[must_use]
426 pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<INT_RAW_SPEC> {
427 CMPR2_TEA_W::new(self, 17)
428 }
429 #[doc = "Bit 18 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEB event"]
430 #[inline(always)]
431 #[must_use]
432 pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<INT_RAW_SPEC> {
433 CMPR0_TEB_W::new(self, 18)
434 }
435 #[doc = "Bit 19 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEB event"]
436 #[inline(always)]
437 #[must_use]
438 pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<INT_RAW_SPEC> {
439 CMPR1_TEB_W::new(self, 19)
440 }
441 #[doc = "Bit 20 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEB event"]
442 #[inline(always)]
443 #[must_use]
444 pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<INT_RAW_SPEC> {
445 CMPR2_TEB_W::new(self, 20)
446 }
447 #[doc = "Bit 21 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
448 #[inline(always)]
449 #[must_use]
450 pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<INT_RAW_SPEC> {
451 TZ0_CBC_W::new(self, 21)
452 }
453 #[doc = "Bit 22 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
454 #[inline(always)]
455 #[must_use]
456 pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<INT_RAW_SPEC> {
457 TZ1_CBC_W::new(self, 22)
458 }
459 #[doc = "Bit 23 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
460 #[inline(always)]
461 #[must_use]
462 pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<INT_RAW_SPEC> {
463 TZ2_CBC_W::new(self, 23)
464 }
465 #[doc = "Bit 24 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM0."]
466 #[inline(always)]
467 #[must_use]
468 pub fn tz0_ost(&mut self) -> TZ0_OST_W<INT_RAW_SPEC> {
469 TZ0_OST_W::new(self, 24)
470 }
471 #[doc = "Bit 25 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM1."]
472 #[inline(always)]
473 #[must_use]
474 pub fn tz1_ost(&mut self) -> TZ1_OST_W<INT_RAW_SPEC> {
475 TZ1_OST_W::new(self, 25)
476 }
477 #[doc = "Bit 26 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM2."]
478 #[inline(always)]
479 #[must_use]
480 pub fn tz2_ost(&mut self) -> TZ2_OST_W<INT_RAW_SPEC> {
481 TZ2_OST_W::new(self, 26)
482 }
483 #[doc = "Bit 27 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP0."]
484 #[inline(always)]
485 #[must_use]
486 pub fn cap0(&mut self) -> CAP0_W<INT_RAW_SPEC> {
487 CAP0_W::new(self, 27)
488 }
489 #[doc = "Bit 28 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP1."]
490 #[inline(always)]
491 #[must_use]
492 pub fn cap1(&mut self) -> CAP1_W<INT_RAW_SPEC> {
493 CAP1_W::new(self, 28)
494 }
495 #[doc = "Bit 29 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP2."]
496 #[inline(always)]
497 #[must_use]
498 pub fn cap2(&mut self) -> CAP2_W<INT_RAW_SPEC> {
499 CAP2_W::new(self, 29)
500 }
501}
502#[doc = "Interrupt raw status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
503pub struct INT_RAW_SPEC;
504impl crate::RegisterSpec for INT_RAW_SPEC {
505 type Ux = u32;
506}
507#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
508impl crate::Readable for INT_RAW_SPEC {}
509#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"]
510impl crate::Writable for INT_RAW_SPEC {
511 type Safety = crate::Unsafe;
512 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
513 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
514}
515#[doc = "`reset()` method sets INT_RAW to value 0"]
516impl crate::Resettable for INT_RAW_SPEC {
517 const RESET_VALUE: u32 = 0;
518}