esp32p4/mcpwm0/
clk_cfg.rs

1#[doc = "Register `CLK_CFG` reader"]
2pub type R = crate::R<CLK_CFG_SPEC>;
3#[doc = "Register `CLK_CFG` writer"]
4pub type W = crate::W<CLK_CFG_SPEC>;
5#[doc = "Field `CLK_PRESCALE` reader - Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)."]
6pub type CLK_PRESCALE_R = crate::FieldReader;
7#[doc = "Field `CLK_PRESCALE` writer - Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)."]
8pub type CLK_PRESCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9impl R {
10    #[doc = "Bits 0:7 - Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)."]
11    #[inline(always)]
12    pub fn clk_prescale(&self) -> CLK_PRESCALE_R {
13        CLK_PRESCALE_R::new((self.bits & 0xff) as u8)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("CLK_CFG")
20            .field(
21                "clk_prescale",
22                &format_args!("{}", self.clk_prescale().bits()),
23            )
24            .finish()
25    }
26}
27#[cfg(feature = "impl-register-debug")]
28impl core::fmt::Debug for crate::generic::Reg<CLK_CFG_SPEC> {
29    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
30        core::fmt::Debug::fmt(&self.read(), f)
31    }
32}
33impl W {
34    #[doc = "Bits 0:7 - Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)."]
35    #[inline(always)]
36    #[must_use]
37    pub fn clk_prescale(&mut self) -> CLK_PRESCALE_W<CLK_CFG_SPEC> {
38        CLK_PRESCALE_W::new(self, 0)
39    }
40}
41#[doc = "PWM clock prescaler register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
42pub struct CLK_CFG_SPEC;
43impl crate::RegisterSpec for CLK_CFG_SPEC {
44    type Ux = u32;
45}
46#[doc = "`read()` method returns [`clk_cfg::R`](R) reader structure"]
47impl crate::Readable for CLK_CFG_SPEC {}
48#[doc = "`write(|w| ..)` method takes [`clk_cfg::W`](W) writer structure"]
49impl crate::Writable for CLK_CFG_SPEC {
50    type Safety = crate::Unsafe;
51    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
52    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
53}
54#[doc = "`reset()` method sets CLK_CFG to value 0"]
55impl crate::Resettable for CLK_CFG_SPEC {
56    const RESET_VALUE: u32 = 0;
57}
esp32p4/mcpwm0/clk_cfg.rs

esp32p4/mcpwm0/
clk_cfg.rs
