esp32p4/mcpwm0/ch/
fh_cfg1.rs

1#[doc = "Register `FH_CFG1` reader"]
2pub type R = crate::R<FH_CFG1_SPEC>;
3#[doc = "Register `FH_CFG1` writer"]
4pub type W = crate::W<FH_CFG1_SPEC>;
5#[doc = "Field `CLR_OST` reader - Configures the generation of software one-shot mode action clear. A toggle (software negate its value) triggers a clear for on going one-shot mode action."]
6pub type CLR_OST_R = crate::BitReader;
7#[doc = "Field `CLR_OST` writer - Configures the generation of software one-shot mode action clear. A toggle (software negate its value) triggers a clear for on going one-shot mode action."]
8pub type CLR_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CBCPULSE` reader - Configures the refresh moment selection of cycle-by-cycle mode action.\\\\0: Select nothing, will not refresh\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP"]
10pub type CBCPULSE_R = crate::FieldReader;
11#[doc = "Field `CBCPULSE` writer - Configures the refresh moment selection of cycle-by-cycle mode action.\\\\0: Select nothing, will not refresh\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP"]
12pub type CBCPULSE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `FORCE_CBC` reader - Configures the generation of software cycle-by-cycle mode action. A toggle (software negate its value) triggers a cycle-by-cycle mode action."]
14pub type FORCE_CBC_R = crate::BitReader;
15#[doc = "Field `FORCE_CBC` writer - Configures the generation of software cycle-by-cycle mode action. A toggle (software negate its value) triggers a cycle-by-cycle mode action."]
16pub type FORCE_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FORCE_OST` reader - Configures the generation of software one-shot mode action. A toggle (software negate its value) triggers a one-shot mode action."]
18pub type FORCE_OST_R = crate::BitReader;
19#[doc = "Field `FORCE_OST` writer - Configures the generation of software one-shot mode action. A toggle (software negate its value) triggers a one-shot mode action."]
20pub type FORCE_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 0 - Configures the generation of software one-shot mode action clear. A toggle (software negate its value) triggers a clear for on going one-shot mode action."]
23    #[inline(always)]
24    pub fn clr_ost(&self) -> CLR_OST_R {
25        CLR_OST_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bits 1:2 - Configures the refresh moment selection of cycle-by-cycle mode action.\\\\0: Select nothing, will not refresh\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP"]
28    #[inline(always)]
29    pub fn cbcpulse(&self) -> CBCPULSE_R {
30        CBCPULSE_R::new(((self.bits >> 1) & 3) as u8)
31    }
32    #[doc = "Bit 3 - Configures the generation of software cycle-by-cycle mode action. A toggle (software negate its value) triggers a cycle-by-cycle mode action."]
33    #[inline(always)]
34    pub fn force_cbc(&self) -> FORCE_CBC_R {
35        FORCE_CBC_R::new(((self.bits >> 3) & 1) != 0)
36    }
37    #[doc = "Bit 4 - Configures the generation of software one-shot mode action. A toggle (software negate its value) triggers a one-shot mode action."]
38    #[inline(always)]
39    pub fn force_ost(&self) -> FORCE_OST_R {
40        FORCE_OST_R::new(((self.bits >> 4) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("FH_CFG1")
47            .field("clr_ost", &format_args!("{}", self.clr_ost().bit()))
48            .field("cbcpulse", &format_args!("{}", self.cbcpulse().bits()))
49            .field("force_cbc", &format_args!("{}", self.force_cbc().bit()))
50            .field("force_ost", &format_args!("{}", self.force_ost().bit()))
51            .finish()
52    }
53}
54#[cfg(feature = "impl-register-debug")]
55impl core::fmt::Debug for crate::generic::Reg<FH_CFG1_SPEC> {
56    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
57        core::fmt::Debug::fmt(&self.read(), f)
58    }
59}
60impl W {
61    #[doc = "Bit 0 - Configures the generation of software one-shot mode action clear. A toggle (software negate its value) triggers a clear for on going one-shot mode action."]
62    #[inline(always)]
63    #[must_use]
64    pub fn clr_ost(&mut self) -> CLR_OST_W<FH_CFG1_SPEC> {
65        CLR_OST_W::new(self, 0)
66    }
67    #[doc = "Bits 1:2 - Configures the refresh moment selection of cycle-by-cycle mode action.\\\\0: Select nothing, will not refresh\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP"]
68    #[inline(always)]
69    #[must_use]
70    pub fn cbcpulse(&mut self) -> CBCPULSE_W<FH_CFG1_SPEC> {
71        CBCPULSE_W::new(self, 1)
72    }
73    #[doc = "Bit 3 - Configures the generation of software cycle-by-cycle mode action. A toggle (software negate its value) triggers a cycle-by-cycle mode action."]
74    #[inline(always)]
75    #[must_use]
76    pub fn force_cbc(&mut self) -> FORCE_CBC_W<FH_CFG1_SPEC> {
77        FORCE_CBC_W::new(self, 3)
78    }
79    #[doc = "Bit 4 - Configures the generation of software one-shot mode action. A toggle (software negate its value) triggers a one-shot mode action."]
80    #[inline(always)]
81    #[must_use]
82    pub fn force_ost(&mut self) -> FORCE_OST_W<FH_CFG1_SPEC> {
83        FORCE_OST_W::new(self, 4)
84    }
85}
86#[doc = "Software triggers for fault handler actions configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fh_cfg1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fh_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
87pub struct FH_CFG1_SPEC;
88impl crate::RegisterSpec for FH_CFG1_SPEC {
89    type Ux = u32;
90}
91#[doc = "`read()` method returns [`fh_cfg1::R`](R) reader structure"]
92impl crate::Readable for FH_CFG1_SPEC {}
93#[doc = "`write(|w| ..)` method takes [`fh_cfg1::W`](W) writer structure"]
94impl crate::Writable for FH_CFG1_SPEC {
95    type Safety = crate::Unsafe;
96    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
97    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
98}
99#[doc = "`reset()` method sets FH_CFG1 to value 0"]
100impl crate::Resettable for FH_CFG1_SPEC {
101    const RESET_VALUE: u32 = 0;
102}
esp32p4/mcpwm0/ch/fh_cfg1.rs

esp32p4/mcpwm0/ch/
fh_cfg1.rs
