esp32p4/lp_adc/
reader1_ctrl.rs

1#[doc = "Register `READER1_CTRL` reader"]
2pub type R = crate::R<READER1_CTRL_SPEC>;
3#[doc = "Register `READER1_CTRL` writer"]
4pub type W = crate::W<READER1_CTRL_SPEC>;
5#[doc = "Field `SAR1_CLK_DIV` reader - Clock divider."]
6pub type SAR1_CLK_DIV_R = crate::FieldReader;
7#[doc = "Field `SAR1_CLK_DIV` writer - Clock divider."]
8pub type SAR1_CLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `SAR1_CLK_GATED` reader - N/A"]
10pub type SAR1_CLK_GATED_R = crate::BitReader;
11#[doc = "Field `SAR1_CLK_GATED` writer - N/A"]
12pub type SAR1_CLK_GATED_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SAR1_SAMPLE_NUM` reader - N/A"]
14pub type SAR1_SAMPLE_NUM_R = crate::FieldReader;
15#[doc = "Field `SAR1_SAMPLE_NUM` writer - N/A"]
16pub type SAR1_SAMPLE_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17#[doc = "Field `SAR1_DATA_INV` reader - Invert SAR ADC1 data."]
18pub type SAR1_DATA_INV_R = crate::BitReader;
19#[doc = "Field `SAR1_DATA_INV` writer - Invert SAR ADC1 data."]
20pub type SAR1_DATA_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `SAR1_INT_EN` reader - Enable saradc1 to send out interrupt."]
22pub type SAR1_INT_EN_R = crate::BitReader;
23#[doc = "Field `SAR1_INT_EN` writer - Enable saradc1 to send out interrupt."]
24pub type SAR1_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SAR1_EN_PAD_FORCE_ENABLE` reader - Force enable adc en_pad to analog circuit 2'b11: force enable ."]
26pub type SAR1_EN_PAD_FORCE_ENABLE_R = crate::FieldReader;
27#[doc = "Field `SAR1_EN_PAD_FORCE_ENABLE` writer - Force enable adc en_pad to analog circuit 2'b11: force enable ."]
28pub type SAR1_EN_PAD_FORCE_ENABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29impl R {
30    #[doc = "Bits 0:7 - Clock divider."]
31    #[inline(always)]
32    pub fn sar1_clk_div(&self) -> SAR1_CLK_DIV_R {
33        SAR1_CLK_DIV_R::new((self.bits & 0xff) as u8)
34    }
35    #[doc = "Bit 18 - N/A"]
36    #[inline(always)]
37    pub fn sar1_clk_gated(&self) -> SAR1_CLK_GATED_R {
38        SAR1_CLK_GATED_R::new(((self.bits >> 18) & 1) != 0)
39    }
40    #[doc = "Bits 19:26 - N/A"]
41    #[inline(always)]
42    pub fn sar1_sample_num(&self) -> SAR1_SAMPLE_NUM_R {
43        SAR1_SAMPLE_NUM_R::new(((self.bits >> 19) & 0xff) as u8)
44    }
45    #[doc = "Bit 28 - Invert SAR ADC1 data."]
46    #[inline(always)]
47    pub fn sar1_data_inv(&self) -> SAR1_DATA_INV_R {
48        SAR1_DATA_INV_R::new(((self.bits >> 28) & 1) != 0)
49    }
50    #[doc = "Bit 29 - Enable saradc1 to send out interrupt."]
51    #[inline(always)]
52    pub fn sar1_int_en(&self) -> SAR1_INT_EN_R {
53        SAR1_INT_EN_R::new(((self.bits >> 29) & 1) != 0)
54    }
55    #[doc = "Bits 30:31 - Force enable adc en_pad to analog circuit 2'b11: force enable ."]
56    #[inline(always)]
57    pub fn sar1_en_pad_force_enable(&self) -> SAR1_EN_PAD_FORCE_ENABLE_R {
58        SAR1_EN_PAD_FORCE_ENABLE_R::new(((self.bits >> 30) & 3) as u8)
59    }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64        f.debug_struct("READER1_CTRL")
65            .field(
66                "sar1_clk_div",
67                &format_args!("{}", self.sar1_clk_div().bits()),
68            )
69            .field(
70                "sar1_clk_gated",
71                &format_args!("{}", self.sar1_clk_gated().bit()),
72            )
73            .field(
74                "sar1_sample_num",
75                &format_args!("{}", self.sar1_sample_num().bits()),
76            )
77            .field(
78                "sar1_data_inv",
79                &format_args!("{}", self.sar1_data_inv().bit()),
80            )
81            .field("sar1_int_en", &format_args!("{}", self.sar1_int_en().bit()))
82            .field(
83                "sar1_en_pad_force_enable",
84                &format_args!("{}", self.sar1_en_pad_force_enable().bits()),
85            )
86            .finish()
87    }
88}
89#[cfg(feature = "impl-register-debug")]
90impl core::fmt::Debug for crate::generic::Reg<READER1_CTRL_SPEC> {
91    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
92        core::fmt::Debug::fmt(&self.read(), f)
93    }
94}
95impl W {
96    #[doc = "Bits 0:7 - Clock divider."]
97    #[inline(always)]
98    #[must_use]
99    pub fn sar1_clk_div(&mut self) -> SAR1_CLK_DIV_W<READER1_CTRL_SPEC> {
100        SAR1_CLK_DIV_W::new(self, 0)
101    }
102    #[doc = "Bit 18 - N/A"]
103    #[inline(always)]
104    #[must_use]
105    pub fn sar1_clk_gated(&mut self) -> SAR1_CLK_GATED_W<READER1_CTRL_SPEC> {
106        SAR1_CLK_GATED_W::new(self, 18)
107    }
108    #[doc = "Bits 19:26 - N/A"]
109    #[inline(always)]
110    #[must_use]
111    pub fn sar1_sample_num(&mut self) -> SAR1_SAMPLE_NUM_W<READER1_CTRL_SPEC> {
112        SAR1_SAMPLE_NUM_W::new(self, 19)
113    }
114    #[doc = "Bit 28 - Invert SAR ADC1 data."]
115    #[inline(always)]
116    #[must_use]
117    pub fn sar1_data_inv(&mut self) -> SAR1_DATA_INV_W<READER1_CTRL_SPEC> {
118        SAR1_DATA_INV_W::new(self, 28)
119    }
120    #[doc = "Bit 29 - Enable saradc1 to send out interrupt."]
121    #[inline(always)]
122    #[must_use]
123    pub fn sar1_int_en(&mut self) -> SAR1_INT_EN_W<READER1_CTRL_SPEC> {
124        SAR1_INT_EN_W::new(self, 29)
125    }
126    #[doc = "Bits 30:31 - Force enable adc en_pad to analog circuit 2'b11: force enable ."]
127    #[inline(always)]
128    #[must_use]
129    pub fn sar1_en_pad_force_enable(&mut self) -> SAR1_EN_PAD_FORCE_ENABLE_W<READER1_CTRL_SPEC> {
130        SAR1_EN_PAD_FORCE_ENABLE_W::new(self, 30)
131    }
132}
133#[doc = "Control the read operation of ADC1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reader1_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reader1_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
134pub struct READER1_CTRL_SPEC;
135impl crate::RegisterSpec for READER1_CTRL_SPEC {
136    type Ux = u32;
137}
138#[doc = "`read()` method returns [`reader1_ctrl::R`](R) reader structure"]
139impl crate::Readable for READER1_CTRL_SPEC {}
140#[doc = "`write(|w| ..)` method takes [`reader1_ctrl::W`](W) writer structure"]
141impl crate::Writable for READER1_CTRL_SPEC {
142    type Safety = crate::Unsafe;
143    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
144    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
145}
146#[doc = "`reset()` method sets READER1_CTRL to value 0x2004_0002"]
147impl crate::Resettable for READER1_CTRL_SPEC {
148    const RESET_VALUE: u32 = 0x2004_0002;
149}
esp32p4/lp_adc/reader1_ctrl.rs

esp32p4/lp_adc/
reader1_ctrl.rs
