esp32p4/jpeg/
decode_conf.rs1#[doc = "Register `DECODE_CONF` reader"]
2pub type R = crate::R<DECODE_CONF_SPEC>;
3#[doc = "Register `DECODE_CONF` writer"]
4pub type W = crate::W<DECODE_CONF_SPEC>;
5#[doc = "Field `RESTART_INTERVAL` reader - configure restart interval in DRI marker when decode"]
6pub type RESTART_INTERVAL_R = crate::FieldReader<u16>;
7#[doc = "Field `RESTART_INTERVAL` writer - configure restart interval in DRI marker when decode"]
8pub type RESTART_INTERVAL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9#[doc = "Field `COMPONENT_NUM` reader - configure number of components in frame when decode"]
10pub type COMPONENT_NUM_R = crate::FieldReader;
11#[doc = "Field `COMPONENT_NUM` writer - configure number of components in frame when decode"]
12pub type COMPONENT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13#[doc = "Field `SW_DHT_EN` reader - software decode dht table enable"]
14pub type SW_DHT_EN_R = crate::BitReader;
15#[doc = "Field `SOS_CHECK_BYTE_NUM` reader - Configure the byte number to check next sos marker in the multi-scan picture after one scan is decoded down. The real check number is reg_sos_check_byte_num+1"]
16pub type SOS_CHECK_BYTE_NUM_R = crate::FieldReader;
17#[doc = "Field `SOS_CHECK_BYTE_NUM` writer - Configure the byte number to check next sos marker in the multi-scan picture after one scan is decoded down. The real check number is reg_sos_check_byte_num+1"]
18pub type SOS_CHECK_BYTE_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
19#[doc = "Field `RST_CHECK_BYTE_NUM` reader - Configure the byte number to check next rst marker after one rst interval is decoded down. The real check number is reg_rst_check_byte_num+1"]
20pub type RST_CHECK_BYTE_NUM_R = crate::FieldReader;
21#[doc = "Field `RST_CHECK_BYTE_NUM` writer - Configure the byte number to check next rst marker after one rst interval is decoded down. The real check number is reg_rst_check_byte_num+1"]
22pub type RST_CHECK_BYTE_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
23#[doc = "Field `MULTI_SCAN_ERR_CHECK` reader - reserved for decoder"]
24pub type MULTI_SCAN_ERR_CHECK_R = crate::BitReader;
25#[doc = "Field `MULTI_SCAN_ERR_CHECK` writer - reserved for decoder"]
26pub type MULTI_SCAN_ERR_CHECK_W<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `DEZIGZAG_READY_CTL` reader - reserved for decoder"]
28pub type DEZIGZAG_READY_CTL_R = crate::BitReader;
29#[doc = "Field `DEZIGZAG_READY_CTL` writer - reserved for decoder"]
30pub type DEZIGZAG_READY_CTL_W<'a, REG> = crate::BitWriter<'a, REG>;
31impl R {
32 #[doc = "Bits 0:15 - configure restart interval in DRI marker when decode"]
33 #[inline(always)]
34 pub fn restart_interval(&self) -> RESTART_INTERVAL_R {
35 RESTART_INTERVAL_R::new((self.bits & 0xffff) as u16)
36 }
37 #[doc = "Bits 16:23 - configure number of components in frame when decode"]
38 #[inline(always)]
39 pub fn component_num(&self) -> COMPONENT_NUM_R {
40 COMPONENT_NUM_R::new(((self.bits >> 16) & 0xff) as u8)
41 }
42 #[doc = "Bit 24 - software decode dht table enable"]
43 #[inline(always)]
44 pub fn sw_dht_en(&self) -> SW_DHT_EN_R {
45 SW_DHT_EN_R::new(((self.bits >> 24) & 1) != 0)
46 }
47 #[doc = "Bits 25:26 - Configure the byte number to check next sos marker in the multi-scan picture after one scan is decoded down. The real check number is reg_sos_check_byte_num+1"]
48 #[inline(always)]
49 pub fn sos_check_byte_num(&self) -> SOS_CHECK_BYTE_NUM_R {
50 SOS_CHECK_BYTE_NUM_R::new(((self.bits >> 25) & 3) as u8)
51 }
52 #[doc = "Bits 27:28 - Configure the byte number to check next rst marker after one rst interval is decoded down. The real check number is reg_rst_check_byte_num+1"]
53 #[inline(always)]
54 pub fn rst_check_byte_num(&self) -> RST_CHECK_BYTE_NUM_R {
55 RST_CHECK_BYTE_NUM_R::new(((self.bits >> 27) & 3) as u8)
56 }
57 #[doc = "Bit 29 - reserved for decoder"]
58 #[inline(always)]
59 pub fn multi_scan_err_check(&self) -> MULTI_SCAN_ERR_CHECK_R {
60 MULTI_SCAN_ERR_CHECK_R::new(((self.bits >> 29) & 1) != 0)
61 }
62 #[doc = "Bit 30 - reserved for decoder"]
63 #[inline(always)]
64 pub fn dezigzag_ready_ctl(&self) -> DEZIGZAG_READY_CTL_R {
65 DEZIGZAG_READY_CTL_R::new(((self.bits >> 30) & 1) != 0)
66 }
67}
68#[cfg(feature = "impl-register-debug")]
69impl core::fmt::Debug for R {
70 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
71 f.debug_struct("DECODE_CONF")
72 .field(
73 "restart_interval",
74 &format_args!("{}", self.restart_interval().bits()),
75 )
76 .field(
77 "component_num",
78 &format_args!("{}", self.component_num().bits()),
79 )
80 .field("sw_dht_en", &format_args!("{}", self.sw_dht_en().bit()))
81 .field(
82 "sos_check_byte_num",
83 &format_args!("{}", self.sos_check_byte_num().bits()),
84 )
85 .field(
86 "rst_check_byte_num",
87 &format_args!("{}", self.rst_check_byte_num().bits()),
88 )
89 .field(
90 "multi_scan_err_check",
91 &format_args!("{}", self.multi_scan_err_check().bit()),
92 )
93 .field(
94 "dezigzag_ready_ctl",
95 &format_args!("{}", self.dezigzag_ready_ctl().bit()),
96 )
97 .finish()
98 }
99}
100#[cfg(feature = "impl-register-debug")]
101impl core::fmt::Debug for crate::generic::Reg<DECODE_CONF_SPEC> {
102 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
103 core::fmt::Debug::fmt(&self.read(), f)
104 }
105}
106impl W {
107 #[doc = "Bits 0:15 - configure restart interval in DRI marker when decode"]
108 #[inline(always)]
109 #[must_use]
110 pub fn restart_interval(&mut self) -> RESTART_INTERVAL_W<DECODE_CONF_SPEC> {
111 RESTART_INTERVAL_W::new(self, 0)
112 }
113 #[doc = "Bits 16:23 - configure number of components in frame when decode"]
114 #[inline(always)]
115 #[must_use]
116 pub fn component_num(&mut self) -> COMPONENT_NUM_W<DECODE_CONF_SPEC> {
117 COMPONENT_NUM_W::new(self, 16)
118 }
119 #[doc = "Bits 25:26 - Configure the byte number to check next sos marker in the multi-scan picture after one scan is decoded down. The real check number is reg_sos_check_byte_num+1"]
120 #[inline(always)]
121 #[must_use]
122 pub fn sos_check_byte_num(&mut self) -> SOS_CHECK_BYTE_NUM_W<DECODE_CONF_SPEC> {
123 SOS_CHECK_BYTE_NUM_W::new(self, 25)
124 }
125 #[doc = "Bits 27:28 - Configure the byte number to check next rst marker after one rst interval is decoded down. The real check number is reg_rst_check_byte_num+1"]
126 #[inline(always)]
127 #[must_use]
128 pub fn rst_check_byte_num(&mut self) -> RST_CHECK_BYTE_NUM_W<DECODE_CONF_SPEC> {
129 RST_CHECK_BYTE_NUM_W::new(self, 27)
130 }
131 #[doc = "Bit 29 - reserved for decoder"]
132 #[inline(always)]
133 #[must_use]
134 pub fn multi_scan_err_check(&mut self) -> MULTI_SCAN_ERR_CHECK_W<DECODE_CONF_SPEC> {
135 MULTI_SCAN_ERR_CHECK_W::new(self, 29)
136 }
137 #[doc = "Bit 30 - reserved for decoder"]
138 #[inline(always)]
139 #[must_use]
140 pub fn dezigzag_ready_ctl(&mut self) -> DEZIGZAG_READY_CTL_W<DECODE_CONF_SPEC> {
141 DEZIGZAG_READY_CTL_W::new(self, 30)
142 }
143}
144#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`decode_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`decode_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
145pub struct DECODE_CONF_SPEC;
146impl crate::RegisterSpec for DECODE_CONF_SPEC {
147 type Ux = u32;
148}
149#[doc = "`read()` method returns [`decode_conf::R`](R) reader structure"]
150impl crate::Readable for DECODE_CONF_SPEC {}
151#[doc = "`write(|w| ..)` method takes [`decode_conf::W`](W) writer structure"]
152impl crate::Writable for DECODE_CONF_SPEC {
153 type Safety = crate::Unsafe;
154 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
155 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
156}
157#[doc = "`reset()` method sets DECODE_CONF to value 0x5f03_0000"]
158impl crate::Resettable for DECODE_CONF_SPEC {
159 const RESET_VALUE: u32 = 0x5f03_0000;
160}