esp32p4/hp_sys_clkrst/
ref_clk_ctrl0.rs

1#[doc = "Register `REF_CLK_CTRL0` reader"]
2pub type R = crate::R<REF_CLK_CTRL0_SPEC>;
3#[doc = "Register `REF_CLK_CTRL0` writer"]
4pub type W = crate::W<REF_CLK_CTRL0_SPEC>;
5#[doc = "Field `REF_50M_CLK_DIV_NUM` reader - Reserved"]
6pub type REF_50M_CLK_DIV_NUM_R = crate::FieldReader;
7#[doc = "Field `REF_50M_CLK_DIV_NUM` writer - Reserved"]
8pub type REF_50M_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `REF_25M_CLK_DIV_NUM` reader - Reserved"]
10pub type REF_25M_CLK_DIV_NUM_R = crate::FieldReader;
11#[doc = "Field `REF_25M_CLK_DIV_NUM` writer - Reserved"]
12pub type REF_25M_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13#[doc = "Field `REF_240M_CLK_DIV_NUM` reader - Reserved"]
14pub type REF_240M_CLK_DIV_NUM_R = crate::FieldReader;
15#[doc = "Field `REF_240M_CLK_DIV_NUM` writer - Reserved"]
16pub type REF_240M_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17#[doc = "Field `REF_160M_CLK_DIV_NUM` reader - Reserved"]
18pub type REF_160M_CLK_DIV_NUM_R = crate::FieldReader;
19#[doc = "Field `REF_160M_CLK_DIV_NUM` writer - Reserved"]
20pub type REF_160M_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
21impl R {
22    #[doc = "Bits 0:7 - Reserved"]
23    #[inline(always)]
24    pub fn ref_50m_clk_div_num(&self) -> REF_50M_CLK_DIV_NUM_R {
25        REF_50M_CLK_DIV_NUM_R::new((self.bits & 0xff) as u8)
26    }
27    #[doc = "Bits 8:15 - Reserved"]
28    #[inline(always)]
29    pub fn ref_25m_clk_div_num(&self) -> REF_25M_CLK_DIV_NUM_R {
30        REF_25M_CLK_DIV_NUM_R::new(((self.bits >> 8) & 0xff) as u8)
31    }
32    #[doc = "Bits 16:23 - Reserved"]
33    #[inline(always)]
34    pub fn ref_240m_clk_div_num(&self) -> REF_240M_CLK_DIV_NUM_R {
35        REF_240M_CLK_DIV_NUM_R::new(((self.bits >> 16) & 0xff) as u8)
36    }
37    #[doc = "Bits 24:31 - Reserved"]
38    #[inline(always)]
39    pub fn ref_160m_clk_div_num(&self) -> REF_160M_CLK_DIV_NUM_R {
40        REF_160M_CLK_DIV_NUM_R::new(((self.bits >> 24) & 0xff) as u8)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("REF_CLK_CTRL0")
47            .field(
48                "ref_50m_clk_div_num",
49                &format_args!("{}", self.ref_50m_clk_div_num().bits()),
50            )
51            .field(
52                "ref_25m_clk_div_num",
53                &format_args!("{}", self.ref_25m_clk_div_num().bits()),
54            )
55            .field(
56                "ref_240m_clk_div_num",
57                &format_args!("{}", self.ref_240m_clk_div_num().bits()),
58            )
59            .field(
60                "ref_160m_clk_div_num",
61                &format_args!("{}", self.ref_160m_clk_div_num().bits()),
62            )
63            .finish()
64    }
65}
66#[cfg(feature = "impl-register-debug")]
67impl core::fmt::Debug for crate::generic::Reg<REF_CLK_CTRL0_SPEC> {
68    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
69        core::fmt::Debug::fmt(&self.read(), f)
70    }
71}
72impl W {
73    #[doc = "Bits 0:7 - Reserved"]
74    #[inline(always)]
75    #[must_use]
76    pub fn ref_50m_clk_div_num(&mut self) -> REF_50M_CLK_DIV_NUM_W<REF_CLK_CTRL0_SPEC> {
77        REF_50M_CLK_DIV_NUM_W::new(self, 0)
78    }
79    #[doc = "Bits 8:15 - Reserved"]
80    #[inline(always)]
81    #[must_use]
82    pub fn ref_25m_clk_div_num(&mut self) -> REF_25M_CLK_DIV_NUM_W<REF_CLK_CTRL0_SPEC> {
83        REF_25M_CLK_DIV_NUM_W::new(self, 8)
84    }
85    #[doc = "Bits 16:23 - Reserved"]
86    #[inline(always)]
87    #[must_use]
88    pub fn ref_240m_clk_div_num(&mut self) -> REF_240M_CLK_DIV_NUM_W<REF_CLK_CTRL0_SPEC> {
89        REF_240M_CLK_DIV_NUM_W::new(self, 16)
90    }
91    #[doc = "Bits 24:31 - Reserved"]
92    #[inline(always)]
93    #[must_use]
94    pub fn ref_160m_clk_div_num(&mut self) -> REF_160M_CLK_DIV_NUM_W<REF_CLK_CTRL0_SPEC> {
95        REF_160M_CLK_DIV_NUM_W::new(self, 24)
96    }
97}
98#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ref_clk_ctrl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ref_clk_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
99pub struct REF_CLK_CTRL0_SPEC;
100impl crate::RegisterSpec for REF_CLK_CTRL0_SPEC {
101    type Ux = u32;
102}
103#[doc = "`read()` method returns [`ref_clk_ctrl0::R`](R) reader structure"]
104impl crate::Readable for REF_CLK_CTRL0_SPEC {}
105#[doc = "`write(|w| ..)` method takes [`ref_clk_ctrl0::W`](W) writer structure"]
106impl crate::Writable for REF_CLK_CTRL0_SPEC {
107    type Safety = crate::Unsafe;
108    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
109    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
110}
111#[doc = "`reset()` method sets REF_CLK_CTRL0 to value 0x0201_1309"]
112impl crate::Resettable for REF_CLK_CTRL0_SPEC {
113    const RESET_VALUE: u32 = 0x0201_1309;
114}
esp32p4/hp_sys_clkrst/ref_clk_ctrl0.rs

esp32p4/hp_sys_clkrst/
ref_clk_ctrl0.rs
