esp32p4/hp_sys_clkrst/
peri_clk_ctrl12.rs

1#[doc = "Register `PERI_CLK_CTRL12` reader"]
2pub type R = crate::R<PERI_CLK_CTRL12_SPEC>;
3#[doc = "Register `PERI_CLK_CTRL12` writer"]
4pub type W = crate::W<PERI_CLK_CTRL12_SPEC>;
5#[doc = "Field `I2S0_RX_DIV_N` reader - Reserved"]
6pub type I2S0_RX_DIV_N_R = crate::FieldReader;
7#[doc = "Field `I2S0_RX_DIV_N` writer - Reserved"]
8pub type I2S0_RX_DIV_N_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `I2S0_RX_DIV_X` reader - Reserved"]
10pub type I2S0_RX_DIV_X_R = crate::FieldReader<u16>;
11#[doc = "Field `I2S0_RX_DIV_X` writer - Reserved"]
12pub type I2S0_RX_DIV_X_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
13#[doc = "Field `I2S0_RX_DIV_Y` reader - Reserved"]
14pub type I2S0_RX_DIV_Y_R = crate::FieldReader<u16>;
15#[doc = "Field `I2S0_RX_DIV_Y` writer - Reserved"]
16pub type I2S0_RX_DIV_Y_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
17impl R {
18    #[doc = "Bits 0:7 - Reserved"]
19    #[inline(always)]
20    pub fn i2s0_rx_div_n(&self) -> I2S0_RX_DIV_N_R {
21        I2S0_RX_DIV_N_R::new((self.bits & 0xff) as u8)
22    }
23    #[doc = "Bits 8:16 - Reserved"]
24    #[inline(always)]
25    pub fn i2s0_rx_div_x(&self) -> I2S0_RX_DIV_X_R {
26        I2S0_RX_DIV_X_R::new(((self.bits >> 8) & 0x01ff) as u16)
27    }
28    #[doc = "Bits 17:25 - Reserved"]
29    #[inline(always)]
30    pub fn i2s0_rx_div_y(&self) -> I2S0_RX_DIV_Y_R {
31        I2S0_RX_DIV_Y_R::new(((self.bits >> 17) & 0x01ff) as u16)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("PERI_CLK_CTRL12")
38            .field(
39                "i2s0_rx_div_n",
40                &format_args!("{}", self.i2s0_rx_div_n().bits()),
41            )
42            .field(
43                "i2s0_rx_div_x",
44                &format_args!("{}", self.i2s0_rx_div_x().bits()),
45            )
46            .field(
47                "i2s0_rx_div_y",
48                &format_args!("{}", self.i2s0_rx_div_y().bits()),
49            )
50            .finish()
51    }
52}
53#[cfg(feature = "impl-register-debug")]
54impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL12_SPEC> {
55    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
56        core::fmt::Debug::fmt(&self.read(), f)
57    }
58}
59impl W {
60    #[doc = "Bits 0:7 - Reserved"]
61    #[inline(always)]
62    #[must_use]
63    pub fn i2s0_rx_div_n(&mut self) -> I2S0_RX_DIV_N_W<PERI_CLK_CTRL12_SPEC> {
64        I2S0_RX_DIV_N_W::new(self, 0)
65    }
66    #[doc = "Bits 8:16 - Reserved"]
67    #[inline(always)]
68    #[must_use]
69    pub fn i2s0_rx_div_x(&mut self) -> I2S0_RX_DIV_X_W<PERI_CLK_CTRL12_SPEC> {
70        I2S0_RX_DIV_X_W::new(self, 8)
71    }
72    #[doc = "Bits 17:25 - Reserved"]
73    #[inline(always)]
74    #[must_use]
75    pub fn i2s0_rx_div_y(&mut self) -> I2S0_RX_DIV_Y_W<PERI_CLK_CTRL12_SPEC> {
76        I2S0_RX_DIV_Y_W::new(self, 17)
77    }
78}
79#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl12::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
80pub struct PERI_CLK_CTRL12_SPEC;
81impl crate::RegisterSpec for PERI_CLK_CTRL12_SPEC {
82    type Ux = u32;
83}
84#[doc = "`read()` method returns [`peri_clk_ctrl12::R`](R) reader structure"]
85impl crate::Readable for PERI_CLK_CTRL12_SPEC {}
86#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl12::W`](W) writer structure"]
87impl crate::Writable for PERI_CLK_CTRL12_SPEC {
88    type Safety = crate::Unsafe;
89    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
90    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
91}
92#[doc = "`reset()` method sets PERI_CLK_CTRL12 to value 0"]
93impl crate::Resettable for PERI_CLK_CTRL12_SPEC {
94    const RESET_VALUE: u32 = 0;
95}
esp32p4/hp_sys_clkrst/peri_clk_ctrl12.rs

esp32p4/hp_sys_clkrst/
peri_clk_ctrl12.rs
