esp32p4/hp_sys_clkrst/
peri_clk_ctrl112.rs

1#[doc = "Register `PERI_CLK_CTRL112` reader"]
2pub type R = crate::R<PERI_CLK_CTRL112_SPEC>;
3#[doc = "Register `PERI_CLK_CTRL112` writer"]
4pub type W = crate::W<PERI_CLK_CTRL112_SPEC>;
5#[doc = "Field `UART1_SCLK_DIV_NUM` reader - Reserved"]
6pub type UART1_SCLK_DIV_NUM_R = crate::FieldReader;
7#[doc = "Field `UART1_SCLK_DIV_NUM` writer - Reserved"]
8pub type UART1_SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `UART1_SCLK_DIV_NUMERATOR` reader - Reserved"]
10pub type UART1_SCLK_DIV_NUMERATOR_R = crate::FieldReader;
11#[doc = "Field `UART1_SCLK_DIV_NUMERATOR` writer - Reserved"]
12pub type UART1_SCLK_DIV_NUMERATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13#[doc = "Field `UART1_SCLK_DIV_DENOMINATOR` reader - Reserved"]
14pub type UART1_SCLK_DIV_DENOMINATOR_R = crate::FieldReader;
15#[doc = "Field `UART1_SCLK_DIV_DENOMINATOR` writer - Reserved"]
16pub type UART1_SCLK_DIV_DENOMINATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17#[doc = "Field `UART2_CLK_SRC_SEL` reader - Reserved"]
18pub type UART2_CLK_SRC_SEL_R = crate::FieldReader;
19#[doc = "Field `UART2_CLK_SRC_SEL` writer - Reserved"]
20pub type UART2_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `UART2_CLK_EN` reader - Reserved"]
22pub type UART2_CLK_EN_R = crate::BitReader;
23#[doc = "Field `UART2_CLK_EN` writer - Reserved"]
24pub type UART2_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    #[doc = "Bits 0:7 - Reserved"]
27    #[inline(always)]
28    pub fn uart1_sclk_div_num(&self) -> UART1_SCLK_DIV_NUM_R {
29        UART1_SCLK_DIV_NUM_R::new((self.bits & 0xff) as u8)
30    }
31    #[doc = "Bits 8:15 - Reserved"]
32    #[inline(always)]
33    pub fn uart1_sclk_div_numerator(&self) -> UART1_SCLK_DIV_NUMERATOR_R {
34        UART1_SCLK_DIV_NUMERATOR_R::new(((self.bits >> 8) & 0xff) as u8)
35    }
36    #[doc = "Bits 16:23 - Reserved"]
37    #[inline(always)]
38    pub fn uart1_sclk_div_denominator(&self) -> UART1_SCLK_DIV_DENOMINATOR_R {
39        UART1_SCLK_DIV_DENOMINATOR_R::new(((self.bits >> 16) & 0xff) as u8)
40    }
41    #[doc = "Bits 24:25 - Reserved"]
42    #[inline(always)]
43    pub fn uart2_clk_src_sel(&self) -> UART2_CLK_SRC_SEL_R {
44        UART2_CLK_SRC_SEL_R::new(((self.bits >> 24) & 3) as u8)
45    }
46    #[doc = "Bit 26 - Reserved"]
47    #[inline(always)]
48    pub fn uart2_clk_en(&self) -> UART2_CLK_EN_R {
49        UART2_CLK_EN_R::new(((self.bits >> 26) & 1) != 0)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("PERI_CLK_CTRL112")
56            .field(
57                "uart1_sclk_div_num",
58                &format_args!("{}", self.uart1_sclk_div_num().bits()),
59            )
60            .field(
61                "uart1_sclk_div_numerator",
62                &format_args!("{}", self.uart1_sclk_div_numerator().bits()),
63            )
64            .field(
65                "uart1_sclk_div_denominator",
66                &format_args!("{}", self.uart1_sclk_div_denominator().bits()),
67            )
68            .field(
69                "uart2_clk_src_sel",
70                &format_args!("{}", self.uart2_clk_src_sel().bits()),
71            )
72            .field(
73                "uart2_clk_en",
74                &format_args!("{}", self.uart2_clk_en().bit()),
75            )
76            .finish()
77    }
78}
79#[cfg(feature = "impl-register-debug")]
80impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL112_SPEC> {
81    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
82        core::fmt::Debug::fmt(&self.read(), f)
83    }
84}
85impl W {
86    #[doc = "Bits 0:7 - Reserved"]
87    #[inline(always)]
88    #[must_use]
89    pub fn uart1_sclk_div_num(&mut self) -> UART1_SCLK_DIV_NUM_W<PERI_CLK_CTRL112_SPEC> {
90        UART1_SCLK_DIV_NUM_W::new(self, 0)
91    }
92    #[doc = "Bits 8:15 - Reserved"]
93    #[inline(always)]
94    #[must_use]
95    pub fn uart1_sclk_div_numerator(
96        &mut self,
97    ) -> UART1_SCLK_DIV_NUMERATOR_W<PERI_CLK_CTRL112_SPEC> {
98        UART1_SCLK_DIV_NUMERATOR_W::new(self, 8)
99    }
100    #[doc = "Bits 16:23 - Reserved"]
101    #[inline(always)]
102    #[must_use]
103    pub fn uart1_sclk_div_denominator(
104        &mut self,
105    ) -> UART1_SCLK_DIV_DENOMINATOR_W<PERI_CLK_CTRL112_SPEC> {
106        UART1_SCLK_DIV_DENOMINATOR_W::new(self, 16)
107    }
108    #[doc = "Bits 24:25 - Reserved"]
109    #[inline(always)]
110    #[must_use]
111    pub fn uart2_clk_src_sel(&mut self) -> UART2_CLK_SRC_SEL_W<PERI_CLK_CTRL112_SPEC> {
112        UART2_CLK_SRC_SEL_W::new(self, 24)
113    }
114    #[doc = "Bit 26 - Reserved"]
115    #[inline(always)]
116    #[must_use]
117    pub fn uart2_clk_en(&mut self) -> UART2_CLK_EN_W<PERI_CLK_CTRL112_SPEC> {
118        UART2_CLK_EN_W::new(self, 26)
119    }
120}
121#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl112::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl112::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
122pub struct PERI_CLK_CTRL112_SPEC;
123impl crate::RegisterSpec for PERI_CLK_CTRL112_SPEC {
124    type Ux = u32;
125}
126#[doc = "`read()` method returns [`peri_clk_ctrl112::R`](R) reader structure"]
127impl crate::Readable for PERI_CLK_CTRL112_SPEC {}
128#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl112::W`](W) writer structure"]
129impl crate::Writable for PERI_CLK_CTRL112_SPEC {
130    type Safety = crate::Unsafe;
131    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
132    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
133}
134#[doc = "`reset()` method sets PERI_CLK_CTRL112 to value 0x0400_0000"]
135impl crate::Resettable for PERI_CLK_CTRL112_SPEC {
136    const RESET_VALUE: u32 = 0x0400_0000;
137}
esp32p4/hp_sys_clkrst/peri_clk_ctrl112.rs

esp32p4/hp_sys_clkrst/
peri_clk_ctrl112.rs
