esp32p4/hp_sys/
psram_flash_addr_interchange.rs

1#[doc = "Register `PSRAM_FLASH_ADDR_INTERCHANGE` reader"]
2pub type R = crate::R<PSRAM_FLASH_ADDR_INTERCHANGE_SPEC>;
3#[doc = "Register `PSRAM_FLASH_ADDR_INTERCHANGE` writer"]
4pub type W = crate::W<PSRAM_FLASH_ADDR_INTERCHANGE_SPEC>;
5#[doc = "Field `CPU` reader - Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu access through cache"]
6pub type CPU_R = crate::BitReader;
7#[doc = "Field `CPU` writer - Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu access through cache"]
8pub type CPU_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `DMA` reader - Set 1 to enable addr interchange between psram and flash in axi matrix when dma device access, lp core access and hp core access through ahb"]
10pub type DMA_R = crate::BitReader;
11#[doc = "Field `DMA` writer - Set 1 to enable addr interchange between psram and flash in axi matrix when dma device access, lp core access and hp core access through ahb"]
12pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    #[doc = "Bit 0 - Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu access through cache"]
15    #[inline(always)]
16    pub fn cpu(&self) -> CPU_R {
17        CPU_R::new((self.bits & 1) != 0)
18    }
19    #[doc = "Bit 1 - Set 1 to enable addr interchange between psram and flash in axi matrix when dma device access, lp core access and hp core access through ahb"]
20    #[inline(always)]
21    pub fn dma(&self) -> DMA_R {
22        DMA_R::new(((self.bits >> 1) & 1) != 0)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("PSRAM_FLASH_ADDR_INTERCHANGE")
29            .field("cpu", &format_args!("{}", self.cpu().bit()))
30            .field("dma", &format_args!("{}", self.dma().bit()))
31            .finish()
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for crate::generic::Reg<PSRAM_FLASH_ADDR_INTERCHANGE_SPEC> {
36    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
37        core::fmt::Debug::fmt(&self.read(), f)
38    }
39}
40impl W {
41    #[doc = "Bit 0 - Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu access through cache"]
42    #[inline(always)]
43    #[must_use]
44    pub fn cpu(&mut self) -> CPU_W<PSRAM_FLASH_ADDR_INTERCHANGE_SPEC> {
45        CPU_W::new(self, 0)
46    }
47    #[doc = "Bit 1 - Set 1 to enable addr interchange between psram and flash in axi matrix when dma device access, lp core access and hp core access through ahb"]
48    #[inline(always)]
49    #[must_use]
50    pub fn dma(&mut self) -> DMA_W<PSRAM_FLASH_ADDR_INTERCHANGE_SPEC> {
51        DMA_W::new(self, 1)
52    }
53}
54#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psram_flash_addr_interchange::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psram_flash_addr_interchange::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
55pub struct PSRAM_FLASH_ADDR_INTERCHANGE_SPEC;
56impl crate::RegisterSpec for PSRAM_FLASH_ADDR_INTERCHANGE_SPEC {
57    type Ux = u32;
58}
59#[doc = "`read()` method returns [`psram_flash_addr_interchange::R`](R) reader structure"]
60impl crate::Readable for PSRAM_FLASH_ADDR_INTERCHANGE_SPEC {}
61#[doc = "`write(|w| ..)` method takes [`psram_flash_addr_interchange::W`](W) writer structure"]
62impl crate::Writable for PSRAM_FLASH_ADDR_INTERCHANGE_SPEC {
63    type Safety = crate::Unsafe;
64    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
65    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
66}
67#[doc = "`reset()` method sets PSRAM_FLASH_ADDR_INTERCHANGE to value 0"]
68impl crate::Resettable for PSRAM_FLASH_ADDR_INTERCHANGE_SPEC {
69    const RESET_VALUE: u32 = 0;
70}
esp32p4/hp_sys/psram_flash_addr_interchange.rs

esp32p4/hp_sys/
psram_flash_addr_interchange.rs
