esp32p4/hp_sys/
l2_mem_int_clr.rs

1#[doc = "Register `L2_MEM_INT_CLR` writer"]
2pub type W = crate::W<L2_MEM_INT_CLR_SPEC>;
3#[doc = "Field `REG_L2_MEM_ECC_ERR_INT_CLR` writer - NA"]
4pub type REG_L2_MEM_ECC_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `REG_L2_MEM_EXCEED_ADDR_INT_CLR` writer - NA"]
6pub type REG_L2_MEM_EXCEED_ADDR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `REG_L2_MEM_ERR_RESP_INT_CLR` writer - NA"]
8pub type REG_L2_MEM_ERR_RESP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[cfg(feature = "impl-register-debug")]
10impl core::fmt::Debug for crate::generic::Reg<L2_MEM_INT_CLR_SPEC> {
11    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
12        write!(f, "(not readable)")
13    }
14}
15impl W {
16    #[doc = "Bit 0 - NA"]
17    #[inline(always)]
18    #[must_use]
19    pub fn reg_l2_mem_ecc_err_int_clr(
20        &mut self,
21    ) -> REG_L2_MEM_ECC_ERR_INT_CLR_W<L2_MEM_INT_CLR_SPEC> {
22        REG_L2_MEM_ECC_ERR_INT_CLR_W::new(self, 0)
23    }
24    #[doc = "Bit 1 - NA"]
25    #[inline(always)]
26    #[must_use]
27    pub fn reg_l2_mem_exceed_addr_int_clr(
28        &mut self,
29    ) -> REG_L2_MEM_EXCEED_ADDR_INT_CLR_W<L2_MEM_INT_CLR_SPEC> {
30        REG_L2_MEM_EXCEED_ADDR_INT_CLR_W::new(self, 1)
31    }
32    #[doc = "Bit 2 - NA"]
33    #[inline(always)]
34    #[must_use]
35    pub fn reg_l2_mem_err_resp_int_clr(
36        &mut self,
37    ) -> REG_L2_MEM_ERR_RESP_INT_CLR_W<L2_MEM_INT_CLR_SPEC> {
38        REG_L2_MEM_ERR_RESP_INT_CLR_W::new(self, 2)
39    }
40}
41#[doc = "NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_mem_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
42pub struct L2_MEM_INT_CLR_SPEC;
43impl crate::RegisterSpec for L2_MEM_INT_CLR_SPEC {
44    type Ux = u32;
45}
46#[doc = "`write(|w| ..)` method takes [`l2_mem_int_clr::W`](W) writer structure"]
47impl crate::Writable for L2_MEM_INT_CLR_SPEC {
48    type Safety = crate::Unsafe;
49    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
50    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
51}
52#[doc = "`reset()` method sets L2_MEM_INT_CLR to value 0"]
53impl crate::Resettable for L2_MEM_INT_CLR_SPEC {
54    const RESET_VALUE: u32 = 0;
55}
esp32p4/hp_sys/l2_mem_int_clr.rs

esp32p4/hp_sys/
l2_mem_int_clr.rs
