esp32p4/h264_dma/in_ch5/
conf0.rs

1#[doc = "Register `CONF0` reader"]
2pub type R = crate::R<CONF0_SPEC>;
3#[doc = "Register `CONF0` writer"]
4pub type W = crate::W<CONF0_SPEC>;
5#[doc = "Field `IN_ECC_AES_EN` reader - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."]
6pub type IN_ECC_AES_EN_R = crate::BitReader;
7#[doc = "Field `IN_ECC_AES_EN` writer - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."]
8pub type IN_ECC_AES_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `IN_MEM_BURST_LENGTH` reader - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"]
10pub type IN_MEM_BURST_LENGTH_R = crate::FieldReader;
11#[doc = "Field `IN_MEM_BURST_LENGTH` writer - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"]
12pub type IN_MEM_BURST_LENGTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13#[doc = "Field `IN_PAGE_BOUND_EN` reader - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"]
14pub type IN_PAGE_BOUND_EN_R = crate::BitReader;
15#[doc = "Field `IN_PAGE_BOUND_EN` writer - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"]
16pub type IN_PAGE_BOUND_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `IN_RST` reader - Write 1 then write 0 to this bit to reset Rx channel"]
18pub type IN_RST_R = crate::BitReader;
19#[doc = "Field `IN_RST` writer - Write 1 then write 0 to this bit to reset Rx channel"]
20pub type IN_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `IN_CMD_DISABLE` reader - Write 1 before reset and write 0 after reset"]
22pub type IN_CMD_DISABLE_R = crate::BitReader;
23#[doc = "Field `IN_CMD_DISABLE` writer - Write 1 before reset and write 0 after reset"]
24pub type IN_CMD_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."]
27    #[inline(always)]
28    pub fn in_ecc_aes_en(&self) -> IN_ECC_AES_EN_R {
29        IN_ECC_AES_EN_R::new(((self.bits >> 3) & 1) != 0)
30    }
31    #[doc = "Bits 6:8 - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"]
32    #[inline(always)]
33    pub fn in_mem_burst_length(&self) -> IN_MEM_BURST_LENGTH_R {
34        IN_MEM_BURST_LENGTH_R::new(((self.bits >> 6) & 7) as u8)
35    }
36    #[doc = "Bit 12 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"]
37    #[inline(always)]
38    pub fn in_page_bound_en(&self) -> IN_PAGE_BOUND_EN_R {
39        IN_PAGE_BOUND_EN_R::new(((self.bits >> 12) & 1) != 0)
40    }
41    #[doc = "Bit 24 - Write 1 then write 0 to this bit to reset Rx channel"]
42    #[inline(always)]
43    pub fn in_rst(&self) -> IN_RST_R {
44        IN_RST_R::new(((self.bits >> 24) & 1) != 0)
45    }
46    #[doc = "Bit 25 - Write 1 before reset and write 0 after reset"]
47    #[inline(always)]
48    pub fn in_cmd_disable(&self) -> IN_CMD_DISABLE_R {
49        IN_CMD_DISABLE_R::new(((self.bits >> 25) & 1) != 0)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("CONF0")
56            .field(
57                "in_ecc_aes_en",
58                &format_args!("{}", self.in_ecc_aes_en().bit()),
59            )
60            .field(
61                "in_mem_burst_length",
62                &format_args!("{}", self.in_mem_burst_length().bits()),
63            )
64            .field(
65                "in_page_bound_en",
66                &format_args!("{}", self.in_page_bound_en().bit()),
67            )
68            .field("in_rst", &format_args!("{}", self.in_rst().bit()))
69            .field(
70                "in_cmd_disable",
71                &format_args!("{}", self.in_cmd_disable().bit()),
72            )
73            .finish()
74    }
75}
76#[cfg(feature = "impl-register-debug")]
77impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
78    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
79        core::fmt::Debug::fmt(&self.read(), f)
80    }
81}
82impl W {
83    #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."]
84    #[inline(always)]
85    #[must_use]
86    pub fn in_ecc_aes_en(&mut self) -> IN_ECC_AES_EN_W<CONF0_SPEC> {
87        IN_ECC_AES_EN_W::new(self, 3)
88    }
89    #[doc = "Bits 6:8 - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"]
90    #[inline(always)]
91    #[must_use]
92    pub fn in_mem_burst_length(&mut self) -> IN_MEM_BURST_LENGTH_W<CONF0_SPEC> {
93        IN_MEM_BURST_LENGTH_W::new(self, 6)
94    }
95    #[doc = "Bit 12 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"]
96    #[inline(always)]
97    #[must_use]
98    pub fn in_page_bound_en(&mut self) -> IN_PAGE_BOUND_EN_W<CONF0_SPEC> {
99        IN_PAGE_BOUND_EN_W::new(self, 12)
100    }
101    #[doc = "Bit 24 - Write 1 then write 0 to this bit to reset Rx channel"]
102    #[inline(always)]
103    #[must_use]
104    pub fn in_rst(&mut self) -> IN_RST_W<CONF0_SPEC> {
105        IN_RST_W::new(self, 24)
106    }
107    #[doc = "Bit 25 - Write 1 before reset and write 0 after reset"]
108    #[inline(always)]
109    #[must_use]
110    pub fn in_cmd_disable(&mut self) -> IN_CMD_DISABLE_W<CONF0_SPEC> {
111        IN_CMD_DISABLE_W::new(self, 25)
112    }
113}
114#[doc = "RX CH5 config0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
115pub struct CONF0_SPEC;
116impl crate::RegisterSpec for CONF0_SPEC {
117    type Ux = u32;
118}
119#[doc = "`read()` method returns [`conf0::R`](R) reader structure"]
120impl crate::Readable for CONF0_SPEC {}
121#[doc = "`write(|w| ..)` method takes [`conf0::W`](W) writer structure"]
122impl crate::Writable for CONF0_SPEC {
123    type Safety = crate::Unsafe;
124    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
125    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
126}
127#[doc = "`reset()` method sets CONF0 to value 0"]
128impl crate::Resettable for CONF0_SPEC {
129    const RESET_VALUE: u32 = 0;
130}
esp32p4/h264_dma/in_ch5/conf0.rs

esp32p4/h264_dma/in_ch5/
conf0.rs
