esp32p4/dma/ch/
axi_qos0.rs

1#[doc = "Register `AXI_QOS0` reader"]
2pub type R = crate::R<AXI_QOS0_SPEC>;
3#[doc = "Register `AXI_QOS0` writer"]
4pub type W = crate::W<AXI_QOS0_SPEC>;
5#[doc = "Field `CH1_AXI_AWQOS` reader - NA"]
6pub type CH1_AXI_AWQOS_R = crate::FieldReader;
7#[doc = "Field `CH1_AXI_AWQOS` writer - NA"]
8pub type CH1_AXI_AWQOS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `CH1_AXI_ARQOS` reader - NA"]
10pub type CH1_AXI_ARQOS_R = crate::FieldReader;
11#[doc = "Field `CH1_AXI_ARQOS` writer - NA"]
12pub type CH1_AXI_ARQOS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13impl R {
14    #[doc = "Bits 0:3 - NA"]
15    #[inline(always)]
16    pub fn ch1_axi_awqos(&self) -> CH1_AXI_AWQOS_R {
17        CH1_AXI_AWQOS_R::new((self.bits & 0x0f) as u8)
18    }
19    #[doc = "Bits 4:7 - NA"]
20    #[inline(always)]
21    pub fn ch1_axi_arqos(&self) -> CH1_AXI_ARQOS_R {
22        CH1_AXI_ARQOS_R::new(((self.bits >> 4) & 0x0f) as u8)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("AXI_QOS0")
29            .field(
30                "ch1_axi_awqos",
31                &format_args!("{}", self.ch1_axi_awqos().bits()),
32            )
33            .field(
34                "ch1_axi_arqos",
35                &format_args!("{}", self.ch1_axi_arqos().bits()),
36            )
37            .finish()
38    }
39}
40#[cfg(feature = "impl-register-debug")]
41impl core::fmt::Debug for crate::generic::Reg<AXI_QOS0_SPEC> {
42    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
43        core::fmt::Debug::fmt(&self.read(), f)
44    }
45}
46impl W {
47    #[doc = "Bits 0:3 - NA"]
48    #[inline(always)]
49    #[must_use]
50    pub fn ch1_axi_awqos(&mut self) -> CH1_AXI_AWQOS_W<AXI_QOS0_SPEC> {
51        CH1_AXI_AWQOS_W::new(self, 0)
52    }
53    #[doc = "Bits 4:7 - NA"]
54    #[inline(always)]
55    #[must_use]
56    pub fn ch1_axi_arqos(&mut self) -> CH1_AXI_ARQOS_W<AXI_QOS0_SPEC> {
57        CH1_AXI_ARQOS_W::new(self, 4)
58    }
59}
60#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_qos0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_qos0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
61pub struct AXI_QOS0_SPEC;
62impl crate::RegisterSpec for AXI_QOS0_SPEC {
63    type Ux = u32;
64}
65#[doc = "`read()` method returns [`axi_qos0::R`](R) reader structure"]
66impl crate::Readable for AXI_QOS0_SPEC {}
67#[doc = "`write(|w| ..)` method takes [`axi_qos0::W`](W) writer structure"]
68impl crate::Writable for AXI_QOS0_SPEC {
69    type Safety = crate::Unsafe;
70    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
71    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
72}
73#[doc = "`reset()` method sets AXI_QOS0 to value 0"]
74impl crate::Resettable for AXI_QOS0_SPEC {
75    const RESET_VALUE: u32 = 0;
76}
esp32p4/dma/ch/axi_qos0.rs

esp32p4/dma/ch/
axi_qos0.rs
