esp32p4/cache/
l2_cache_access_attr_ctrl.rs

1#[doc = "Register `L2_CACHE_ACCESS_ATTR_CTRL` reader"]
2pub type R = crate::R<L2_CACHE_ACCESS_ATTR_CTRL_SPEC>;
3#[doc = "Register `L2_CACHE_ACCESS_ATTR_CTRL` writer"]
4pub type W = crate::W<L2_CACHE_ACCESS_ATTR_CTRL_SPEC>;
5#[doc = "Field `L2_CACHE_ACCESS_FORCE_CC` reader - Set this bit to force the request to l2 cache with cacheable attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of cacheable and non-cacheable."]
6pub type L2_CACHE_ACCESS_FORCE_CC_R = crate::BitReader;
7#[doc = "Field `L2_CACHE_ACCESS_FORCE_CC` writer - Set this bit to force the request to l2 cache with cacheable attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of cacheable and non-cacheable."]
8pub type L2_CACHE_ACCESS_FORCE_CC_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `L2_CACHE_ACCESS_FORCE_WB` reader - Set this bit to force the request to l2 cache with write-back attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-back and write-through."]
10pub type L2_CACHE_ACCESS_FORCE_WB_R = crate::BitReader;
11#[doc = "Field `L2_CACHE_ACCESS_FORCE_WB` writer - Set this bit to force the request to l2 cache with write-back attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-back and write-through."]
12pub type L2_CACHE_ACCESS_FORCE_WB_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `L2_CACHE_ACCESS_FORCE_WMA` reader - Set this bit to force the request to l2 cache with write-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-miss-allocate and write-miss-no-allocate."]
14pub type L2_CACHE_ACCESS_FORCE_WMA_R = crate::BitReader;
15#[doc = "Field `L2_CACHE_ACCESS_FORCE_WMA` writer - Set this bit to force the request to l2 cache with write-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-miss-allocate and write-miss-no-allocate."]
16pub type L2_CACHE_ACCESS_FORCE_WMA_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `L2_CACHE_ACCESS_FORCE_RMA` reader - Set this bit to force the request to l2 cache with read-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of read-miss-allocate and read-miss-no-allocate."]
18pub type L2_CACHE_ACCESS_FORCE_RMA_R = crate::BitReader;
19#[doc = "Field `L2_CACHE_ACCESS_FORCE_RMA` writer - Set this bit to force the request to l2 cache with read-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of read-miss-allocate and read-miss-no-allocate."]
20pub type L2_CACHE_ACCESS_FORCE_RMA_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 0 - Set this bit to force the request to l2 cache with cacheable attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of cacheable and non-cacheable."]
23    #[inline(always)]
24    pub fn l2_cache_access_force_cc(&self) -> L2_CACHE_ACCESS_FORCE_CC_R {
25        L2_CACHE_ACCESS_FORCE_CC_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - Set this bit to force the request to l2 cache with write-back attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-back and write-through."]
28    #[inline(always)]
29    pub fn l2_cache_access_force_wb(&self) -> L2_CACHE_ACCESS_FORCE_WB_R {
30        L2_CACHE_ACCESS_FORCE_WB_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 2 - Set this bit to force the request to l2 cache with write-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-miss-allocate and write-miss-no-allocate."]
33    #[inline(always)]
34    pub fn l2_cache_access_force_wma(&self) -> L2_CACHE_ACCESS_FORCE_WMA_R {
35        L2_CACHE_ACCESS_FORCE_WMA_R::new(((self.bits >> 2) & 1) != 0)
36    }
37    #[doc = "Bit 3 - Set this bit to force the request to l2 cache with read-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of read-miss-allocate and read-miss-no-allocate."]
38    #[inline(always)]
39    pub fn l2_cache_access_force_rma(&self) -> L2_CACHE_ACCESS_FORCE_RMA_R {
40        L2_CACHE_ACCESS_FORCE_RMA_R::new(((self.bits >> 3) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("L2_CACHE_ACCESS_ATTR_CTRL")
47            .field(
48                "l2_cache_access_force_cc",
49                &format_args!("{}", self.l2_cache_access_force_cc().bit()),
50            )
51            .field(
52                "l2_cache_access_force_wb",
53                &format_args!("{}", self.l2_cache_access_force_wb().bit()),
54            )
55            .field(
56                "l2_cache_access_force_wma",
57                &format_args!("{}", self.l2_cache_access_force_wma().bit()),
58            )
59            .field(
60                "l2_cache_access_force_rma",
61                &format_args!("{}", self.l2_cache_access_force_rma().bit()),
62            )
63            .finish()
64    }
65}
66#[cfg(feature = "impl-register-debug")]
67impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACCESS_ATTR_CTRL_SPEC> {
68    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
69        core::fmt::Debug::fmt(&self.read(), f)
70    }
71}
72impl W {
73    #[doc = "Bit 0 - Set this bit to force the request to l2 cache with cacheable attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of cacheable and non-cacheable."]
74    #[inline(always)]
75    #[must_use]
76    pub fn l2_cache_access_force_cc(
77        &mut self,
78    ) -> L2_CACHE_ACCESS_FORCE_CC_W<L2_CACHE_ACCESS_ATTR_CTRL_SPEC> {
79        L2_CACHE_ACCESS_FORCE_CC_W::new(self, 0)
80    }
81    #[doc = "Bit 1 - Set this bit to force the request to l2 cache with write-back attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-back and write-through."]
82    #[inline(always)]
83    #[must_use]
84    pub fn l2_cache_access_force_wb(
85        &mut self,
86    ) -> L2_CACHE_ACCESS_FORCE_WB_W<L2_CACHE_ACCESS_ATTR_CTRL_SPEC> {
87        L2_CACHE_ACCESS_FORCE_WB_W::new(self, 1)
88    }
89    #[doc = "Bit 2 - Set this bit to force the request to l2 cache with write-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-miss-allocate and write-miss-no-allocate."]
90    #[inline(always)]
91    #[must_use]
92    pub fn l2_cache_access_force_wma(
93        &mut self,
94    ) -> L2_CACHE_ACCESS_FORCE_WMA_W<L2_CACHE_ACCESS_ATTR_CTRL_SPEC> {
95        L2_CACHE_ACCESS_FORCE_WMA_W::new(self, 2)
96    }
97    #[doc = "Bit 3 - Set this bit to force the request to l2 cache with read-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of read-miss-allocate and read-miss-no-allocate."]
98    #[inline(always)]
99    #[must_use]
100    pub fn l2_cache_access_force_rma(
101        &mut self,
102    ) -> L2_CACHE_ACCESS_FORCE_RMA_W<L2_CACHE_ACCESS_ATTR_CTRL_SPEC> {
103        L2_CACHE_ACCESS_FORCE_RMA_W::new(self, 3)
104    }
105}
106#[doc = "L2 cache access attribute control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_access_attr_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_access_attr_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
107pub struct L2_CACHE_ACCESS_ATTR_CTRL_SPEC;
108impl crate::RegisterSpec for L2_CACHE_ACCESS_ATTR_CTRL_SPEC {
109    type Ux = u32;
110}
111#[doc = "`read()` method returns [`l2_cache_access_attr_ctrl::R`](R) reader structure"]
112impl crate::Readable for L2_CACHE_ACCESS_ATTR_CTRL_SPEC {}
113#[doc = "`write(|w| ..)` method takes [`l2_cache_access_attr_ctrl::W`](W) writer structure"]
114impl crate::Writable for L2_CACHE_ACCESS_ATTR_CTRL_SPEC {
115    type Safety = crate::Unsafe;
116    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
117    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
118}
119#[doc = "`reset()` method sets L2_CACHE_ACCESS_ATTR_CTRL to value 0x0f"]
120impl crate::Resettable for L2_CACHE_ACCESS_ATTR_CTRL_SPEC {
121    const RESET_VALUE: u32 = 0x0f;
122}
esp32p4/cache/l2_cache_access_attr_ctrl.rs

esp32p4/cache/
l2_cache_access_attr_ctrl.rs
