esp32p4/axi_dma/out_ch/
out_conf0.rs1#[doc = "Register `OUT_CONF0` reader"]
2pub type R = crate::R<OUT_CONF0_SPEC>;
3#[doc = "Register `OUT_CONF0` writer"]
4pub type W = crate::W<OUT_CONF0_SPEC>;
5#[doc = "Field `OUT_RST_` reader - This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer."]
6pub type OUT_RST__R = crate::BitReader;
7#[doc = "Field `OUT_RST_` writer - This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer."]
8pub type OUT_RST__W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `OUT_LOOP_TEST` reader - reserved"]
10pub type OUT_LOOP_TEST_R = crate::BitReader;
11#[doc = "Field `OUT_LOOP_TEST` writer - reserved"]
12pub type OUT_LOOP_TEST_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `OUT_AUTO_WRBACK` reader - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."]
14pub type OUT_AUTO_WRBACK_R = crate::BitReader;
15#[doc = "Field `OUT_AUTO_WRBACK` writer - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."]
16pub type OUT_AUTO_WRBACK_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `OUT_EOF_MODE` reader - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is generated when data need to transmit has been popped from FIFO in AXI_DMA"]
18pub type OUT_EOF_MODE_R = crate::BitReader;
19#[doc = "Field `OUT_EOF_MODE` writer - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is generated when data need to transmit has been popped from FIFO in AXI_DMA"]
20pub type OUT_EOF_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `OUT_ETM_EN` reader - Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm task."]
22pub type OUT_ETM_EN_R = crate::BitReader;
23#[doc = "Field `OUT_ETM_EN` writer - Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm task."]
24pub type OUT_ETM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `OUT_BURST_SIZE_SEL` reader - 3'b000-3'b100:burst length 8byte~128byte"]
26pub type OUT_BURST_SIZE_SEL_R = crate::FieldReader;
27#[doc = "Field `OUT_BURST_SIZE_SEL` writer - 3'b000-3'b100:burst length 8byte~128byte"]
28pub type OUT_BURST_SIZE_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
29#[doc = "Field `OUT_CMD_DISABLE` reader - 1:mean disable cmd of this ch0"]
30pub type OUT_CMD_DISABLE_R = crate::BitReader;
31#[doc = "Field `OUT_CMD_DISABLE` writer - 1:mean disable cmd of this ch0"]
32pub type OUT_CMD_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `OUT_ECC_AEC_EN` reader - 1: mean access ecc or aes domain,0: mean not"]
34pub type OUT_ECC_AEC_EN_R = crate::BitReader;
35#[doc = "Field `OUT_ECC_AEC_EN` writer - 1: mean access ecc or aes domain,0: mean not"]
36pub type OUT_ECC_AEC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `OUTDSCR_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link descriptor when accessing internal SRAM."]
38pub type OUTDSCR_BURST_EN_R = crate::BitReader;
39#[doc = "Field `OUTDSCR_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link descriptor when accessing internal SRAM."]
40pub type OUTDSCR_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41impl R {
42 #[doc = "Bit 0 - This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer."]
43 #[inline(always)]
44 pub fn out_rst_(&self) -> OUT_RST__R {
45 OUT_RST__R::new((self.bits & 1) != 0)
46 }
47 #[doc = "Bit 1 - reserved"]
48 #[inline(always)]
49 pub fn out_loop_test(&self) -> OUT_LOOP_TEST_R {
50 OUT_LOOP_TEST_R::new(((self.bits >> 1) & 1) != 0)
51 }
52 #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."]
53 #[inline(always)]
54 pub fn out_auto_wrback(&self) -> OUT_AUTO_WRBACK_R {
55 OUT_AUTO_WRBACK_R::new(((self.bits >> 2) & 1) != 0)
56 }
57 #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is generated when data need to transmit has been popped from FIFO in AXI_DMA"]
58 #[inline(always)]
59 pub fn out_eof_mode(&self) -> OUT_EOF_MODE_R {
60 OUT_EOF_MODE_R::new(((self.bits >> 3) & 1) != 0)
61 }
62 #[doc = "Bit 4 - Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm task."]
63 #[inline(always)]
64 pub fn out_etm_en(&self) -> OUT_ETM_EN_R {
65 OUT_ETM_EN_R::new(((self.bits >> 4) & 1) != 0)
66 }
67 #[doc = "Bits 5:7 - 3'b000-3'b100:burst length 8byte~128byte"]
68 #[inline(always)]
69 pub fn out_burst_size_sel(&self) -> OUT_BURST_SIZE_SEL_R {
70 OUT_BURST_SIZE_SEL_R::new(((self.bits >> 5) & 7) as u8)
71 }
72 #[doc = "Bit 8 - 1:mean disable cmd of this ch0"]
73 #[inline(always)]
74 pub fn out_cmd_disable(&self) -> OUT_CMD_DISABLE_R {
75 OUT_CMD_DISABLE_R::new(((self.bits >> 8) & 1) != 0)
76 }
77 #[doc = "Bit 9 - 1: mean access ecc or aes domain,0: mean not"]
78 #[inline(always)]
79 pub fn out_ecc_aec_en(&self) -> OUT_ECC_AEC_EN_R {
80 OUT_ECC_AEC_EN_R::new(((self.bits >> 9) & 1) != 0)
81 }
82 #[doc = "Bit 10 - Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link descriptor when accessing internal SRAM."]
83 #[inline(always)]
84 pub fn outdscr_burst_en(&self) -> OUTDSCR_BURST_EN_R {
85 OUTDSCR_BURST_EN_R::new(((self.bits >> 10) & 1) != 0)
86 }
87}
88#[cfg(feature = "impl-register-debug")]
89impl core::fmt::Debug for R {
90 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91 f.debug_struct("OUT_CONF0")
92 .field("out_rst_", &format_args!("{}", self.out_rst_().bit()))
93 .field(
94 "out_loop_test",
95 &format_args!("{}", self.out_loop_test().bit()),
96 )
97 .field(
98 "out_auto_wrback",
99 &format_args!("{}", self.out_auto_wrback().bit()),
100 )
101 .field(
102 "out_eof_mode",
103 &format_args!("{}", self.out_eof_mode().bit()),
104 )
105 .field("out_etm_en", &format_args!("{}", self.out_etm_en().bit()))
106 .field(
107 "out_burst_size_sel",
108 &format_args!("{}", self.out_burst_size_sel().bits()),
109 )
110 .field(
111 "out_cmd_disable",
112 &format_args!("{}", self.out_cmd_disable().bit()),
113 )
114 .field(
115 "out_ecc_aec_en",
116 &format_args!("{}", self.out_ecc_aec_en().bit()),
117 )
118 .field(
119 "outdscr_burst_en",
120 &format_args!("{}", self.outdscr_burst_en().bit()),
121 )
122 .finish()
123 }
124}
125#[cfg(feature = "impl-register-debug")]
126impl core::fmt::Debug for crate::generic::Reg<OUT_CONF0_SPEC> {
127 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
128 core::fmt::Debug::fmt(&self.read(), f)
129 }
130}
131impl W {
132 #[doc = "Bit 0 - This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer."]
133 #[inline(always)]
134 #[must_use]
135 pub fn out_rst_(&mut self) -> OUT_RST__W<OUT_CONF0_SPEC> {
136 OUT_RST__W::new(self, 0)
137 }
138 #[doc = "Bit 1 - reserved"]
139 #[inline(always)]
140 #[must_use]
141 pub fn out_loop_test(&mut self) -> OUT_LOOP_TEST_W<OUT_CONF0_SPEC> {
142 OUT_LOOP_TEST_W::new(self, 1)
143 }
144 #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."]
145 #[inline(always)]
146 #[must_use]
147 pub fn out_auto_wrback(&mut self) -> OUT_AUTO_WRBACK_W<OUT_CONF0_SPEC> {
148 OUT_AUTO_WRBACK_W::new(self, 2)
149 }
150 #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is generated when data need to transmit has been popped from FIFO in AXI_DMA"]
151 #[inline(always)]
152 #[must_use]
153 pub fn out_eof_mode(&mut self) -> OUT_EOF_MODE_W<OUT_CONF0_SPEC> {
154 OUT_EOF_MODE_W::new(self, 3)
155 }
156 #[doc = "Bit 4 - Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm task."]
157 #[inline(always)]
158 #[must_use]
159 pub fn out_etm_en(&mut self) -> OUT_ETM_EN_W<OUT_CONF0_SPEC> {
160 OUT_ETM_EN_W::new(self, 4)
161 }
162 #[doc = "Bits 5:7 - 3'b000-3'b100:burst length 8byte~128byte"]
163 #[inline(always)]
164 #[must_use]
165 pub fn out_burst_size_sel(&mut self) -> OUT_BURST_SIZE_SEL_W<OUT_CONF0_SPEC> {
166 OUT_BURST_SIZE_SEL_W::new(self, 5)
167 }
168 #[doc = "Bit 8 - 1:mean disable cmd of this ch0"]
169 #[inline(always)]
170 #[must_use]
171 pub fn out_cmd_disable(&mut self) -> OUT_CMD_DISABLE_W<OUT_CONF0_SPEC> {
172 OUT_CMD_DISABLE_W::new(self, 8)
173 }
174 #[doc = "Bit 9 - 1: mean access ecc or aes domain,0: mean not"]
175 #[inline(always)]
176 #[must_use]
177 pub fn out_ecc_aec_en(&mut self) -> OUT_ECC_AEC_EN_W<OUT_CONF0_SPEC> {
178 OUT_ECC_AEC_EN_W::new(self, 9)
179 }
180 #[doc = "Bit 10 - Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link descriptor when accessing internal SRAM."]
181 #[inline(always)]
182 #[must_use]
183 pub fn outdscr_burst_en(&mut self) -> OUTDSCR_BURST_EN_W<OUT_CONF0_SPEC> {
184 OUTDSCR_BURST_EN_W::new(self, 10)
185 }
186}
187#[doc = "Configure 0 register of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
188pub struct OUT_CONF0_SPEC;
189impl crate::RegisterSpec for OUT_CONF0_SPEC {
190 type Ux = u32;
191}
192#[doc = "`read()` method returns [`out_conf0::R`](R) reader structure"]
193impl crate::Readable for OUT_CONF0_SPEC {}
194#[doc = "`write(|w| ..)` method takes [`out_conf0::W`](W) writer structure"]
195impl crate::Writable for OUT_CONF0_SPEC {
196 type Safety = crate::Unsafe;
197 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
198 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
199}
200#[doc = "`reset()` method sets OUT_CONF0 to value 0x08"]
201impl crate::Resettable for OUT_CONF0_SPEC {
202 const RESET_VALUE: u32 = 0x08;
203}