esp32p4/assist_debug/
core_1_intr_rls.rs

1#[doc = "Register `CORE_1_INTR_RLS` reader"]
2pub type R = crate::R<CORE_1_INTR_RLS_SPEC>;
3#[doc = "Register `CORE_1_INTR_RLS` writer"]
4pub type W = crate::W<CORE_1_INTR_RLS_SPEC>;
5#[doc = "Field `CORE_1_AREA_DRAM0_0_RD_RLS` reader - Core1 dram0 area0 read monitor interrupt enable"]
6pub type CORE_1_AREA_DRAM0_0_RD_RLS_R = crate::BitReader;
7#[doc = "Field `CORE_1_AREA_DRAM0_0_RD_RLS` writer - Core1 dram0 area0 read monitor interrupt enable"]
8pub type CORE_1_AREA_DRAM0_0_RD_RLS_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CORE_1_AREA_DRAM0_0_WR_RLS` reader - Core1 dram0 area0 write monitor interrupt enable"]
10pub type CORE_1_AREA_DRAM0_0_WR_RLS_R = crate::BitReader;
11#[doc = "Field `CORE_1_AREA_DRAM0_0_WR_RLS` writer - Core1 dram0 area0 write monitor interrupt enable"]
12pub type CORE_1_AREA_DRAM0_0_WR_RLS_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CORE_1_AREA_DRAM0_1_RD_RLS` reader - Core1 dram0 area1 read monitor interrupt enable"]
14pub type CORE_1_AREA_DRAM0_1_RD_RLS_R = crate::BitReader;
15#[doc = "Field `CORE_1_AREA_DRAM0_1_RD_RLS` writer - Core1 dram0 area1 read monitor interrupt enable"]
16pub type CORE_1_AREA_DRAM0_1_RD_RLS_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CORE_1_AREA_DRAM0_1_WR_RLS` reader - Core1 dram0 area1 write monitor interrupt enable"]
18pub type CORE_1_AREA_DRAM0_1_WR_RLS_R = crate::BitReader;
19#[doc = "Field `CORE_1_AREA_DRAM0_1_WR_RLS` writer - Core1 dram0 area1 write monitor interrupt enable"]
20pub type CORE_1_AREA_DRAM0_1_WR_RLS_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CORE_1_AREA_PIF_0_RD_RLS` reader - Core1 PIF area0 read monitor interrupt enable"]
22pub type CORE_1_AREA_PIF_0_RD_RLS_R = crate::BitReader;
23#[doc = "Field `CORE_1_AREA_PIF_0_RD_RLS` writer - Core1 PIF area0 read monitor interrupt enable"]
24pub type CORE_1_AREA_PIF_0_RD_RLS_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CORE_1_AREA_PIF_0_WR_RLS` reader - Core1 PIF area0 write monitor interrupt enable"]
26pub type CORE_1_AREA_PIF_0_WR_RLS_R = crate::BitReader;
27#[doc = "Field `CORE_1_AREA_PIF_0_WR_RLS` writer - Core1 PIF area0 write monitor interrupt enable"]
28pub type CORE_1_AREA_PIF_0_WR_RLS_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `CORE_1_AREA_PIF_1_RD_RLS` reader - Core1 PIF area1 read monitor interrupt enable"]
30pub type CORE_1_AREA_PIF_1_RD_RLS_R = crate::BitReader;
31#[doc = "Field `CORE_1_AREA_PIF_1_RD_RLS` writer - Core1 PIF area1 read monitor interrupt enable"]
32pub type CORE_1_AREA_PIF_1_RD_RLS_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `CORE_1_AREA_PIF_1_WR_RLS` reader - Core1 PIF area1 write monitor interrupt enable"]
34pub type CORE_1_AREA_PIF_1_WR_RLS_R = crate::BitReader;
35#[doc = "Field `CORE_1_AREA_PIF_1_WR_RLS` writer - Core1 PIF area1 write monitor interrupt enable"]
36pub type CORE_1_AREA_PIF_1_WR_RLS_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `CORE_1_SP_SPILL_MIN_RLS` reader - Core1 stackpoint underflow monitor interrupt enable"]
38pub type CORE_1_SP_SPILL_MIN_RLS_R = crate::BitReader;
39#[doc = "Field `CORE_1_SP_SPILL_MIN_RLS` writer - Core1 stackpoint underflow monitor interrupt enable"]
40pub type CORE_1_SP_SPILL_MIN_RLS_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `CORE_1_SP_SPILL_MAX_RLS` reader - Core1 stackpoint overflow monitor interrupt enable"]
42pub type CORE_1_SP_SPILL_MAX_RLS_R = crate::BitReader;
43#[doc = "Field `CORE_1_SP_SPILL_MAX_RLS` writer - Core1 stackpoint overflow monitor interrupt enable"]
44pub type CORE_1_SP_SPILL_MAX_RLS_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `CORE_1_IRAM0_EXCEPTION_MONITOR_RLS` reader - IBUS busy monitor interrupt enable"]
46pub type CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_R = crate::BitReader;
47#[doc = "Field `CORE_1_IRAM0_EXCEPTION_MONITOR_RLS` writer - IBUS busy monitor interrupt enable"]
48pub type CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `CORE_1_DRAM0_EXCEPTION_MONITOR_RLS` reader - DBUS busy monitor interrupt enbale"]
50pub type CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_R = crate::BitReader;
51#[doc = "Field `CORE_1_DRAM0_EXCEPTION_MONITOR_RLS` writer - DBUS busy monitor interrupt enbale"]
52pub type CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_W<'a, REG> = crate::BitWriter<'a, REG>;
53impl R {
54    #[doc = "Bit 0 - Core1 dram0 area0 read monitor interrupt enable"]
55    #[inline(always)]
56    pub fn core_1_area_dram0_0_rd_rls(&self) -> CORE_1_AREA_DRAM0_0_RD_RLS_R {
57        CORE_1_AREA_DRAM0_0_RD_RLS_R::new((self.bits & 1) != 0)
58    }
59    #[doc = "Bit 1 - Core1 dram0 area0 write monitor interrupt enable"]
60    #[inline(always)]
61    pub fn core_1_area_dram0_0_wr_rls(&self) -> CORE_1_AREA_DRAM0_0_WR_RLS_R {
62        CORE_1_AREA_DRAM0_0_WR_RLS_R::new(((self.bits >> 1) & 1) != 0)
63    }
64    #[doc = "Bit 2 - Core1 dram0 area1 read monitor interrupt enable"]
65    #[inline(always)]
66    pub fn core_1_area_dram0_1_rd_rls(&self) -> CORE_1_AREA_DRAM0_1_RD_RLS_R {
67        CORE_1_AREA_DRAM0_1_RD_RLS_R::new(((self.bits >> 2) & 1) != 0)
68    }
69    #[doc = "Bit 3 - Core1 dram0 area1 write monitor interrupt enable"]
70    #[inline(always)]
71    pub fn core_1_area_dram0_1_wr_rls(&self) -> CORE_1_AREA_DRAM0_1_WR_RLS_R {
72        CORE_1_AREA_DRAM0_1_WR_RLS_R::new(((self.bits >> 3) & 1) != 0)
73    }
74    #[doc = "Bit 4 - Core1 PIF area0 read monitor interrupt enable"]
75    #[inline(always)]
76    pub fn core_1_area_pif_0_rd_rls(&self) -> CORE_1_AREA_PIF_0_RD_RLS_R {
77        CORE_1_AREA_PIF_0_RD_RLS_R::new(((self.bits >> 4) & 1) != 0)
78    }
79    #[doc = "Bit 5 - Core1 PIF area0 write monitor interrupt enable"]
80    #[inline(always)]
81    pub fn core_1_area_pif_0_wr_rls(&self) -> CORE_1_AREA_PIF_0_WR_RLS_R {
82        CORE_1_AREA_PIF_0_WR_RLS_R::new(((self.bits >> 5) & 1) != 0)
83    }
84    #[doc = "Bit 6 - Core1 PIF area1 read monitor interrupt enable"]
85    #[inline(always)]
86    pub fn core_1_area_pif_1_rd_rls(&self) -> CORE_1_AREA_PIF_1_RD_RLS_R {
87        CORE_1_AREA_PIF_1_RD_RLS_R::new(((self.bits >> 6) & 1) != 0)
88    }
89    #[doc = "Bit 7 - Core1 PIF area1 write monitor interrupt enable"]
90    #[inline(always)]
91    pub fn core_1_area_pif_1_wr_rls(&self) -> CORE_1_AREA_PIF_1_WR_RLS_R {
92        CORE_1_AREA_PIF_1_WR_RLS_R::new(((self.bits >> 7) & 1) != 0)
93    }
94    #[doc = "Bit 8 - Core1 stackpoint underflow monitor interrupt enable"]
95    #[inline(always)]
96    pub fn core_1_sp_spill_min_rls(&self) -> CORE_1_SP_SPILL_MIN_RLS_R {
97        CORE_1_SP_SPILL_MIN_RLS_R::new(((self.bits >> 8) & 1) != 0)
98    }
99    #[doc = "Bit 9 - Core1 stackpoint overflow monitor interrupt enable"]
100    #[inline(always)]
101    pub fn core_1_sp_spill_max_rls(&self) -> CORE_1_SP_SPILL_MAX_RLS_R {
102        CORE_1_SP_SPILL_MAX_RLS_R::new(((self.bits >> 9) & 1) != 0)
103    }
104    #[doc = "Bit 10 - IBUS busy monitor interrupt enable"]
105    #[inline(always)]
106    pub fn core_1_iram0_exception_monitor_rls(&self) -> CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_R {
107        CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_R::new(((self.bits >> 10) & 1) != 0)
108    }
109    #[doc = "Bit 11 - DBUS busy monitor interrupt enbale"]
110    #[inline(always)]
111    pub fn core_1_dram0_exception_monitor_rls(&self) -> CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_R {
112        CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_R::new(((self.bits >> 11) & 1) != 0)
113    }
114}
115#[cfg(feature = "impl-register-debug")]
116impl core::fmt::Debug for R {
117    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
118        f.debug_struct("CORE_1_INTR_RLS")
119            .field(
120                "core_1_area_dram0_0_rd_rls",
121                &format_args!("{}", self.core_1_area_dram0_0_rd_rls().bit()),
122            )
123            .field(
124                "core_1_area_dram0_0_wr_rls",
125                &format_args!("{}", self.core_1_area_dram0_0_wr_rls().bit()),
126            )
127            .field(
128                "core_1_area_dram0_1_rd_rls",
129                &format_args!("{}", self.core_1_area_dram0_1_rd_rls().bit()),
130            )
131            .field(
132                "core_1_area_dram0_1_wr_rls",
133                &format_args!("{}", self.core_1_area_dram0_1_wr_rls().bit()),
134            )
135            .field(
136                "core_1_area_pif_0_rd_rls",
137                &format_args!("{}", self.core_1_area_pif_0_rd_rls().bit()),
138            )
139            .field(
140                "core_1_area_pif_0_wr_rls",
141                &format_args!("{}", self.core_1_area_pif_0_wr_rls().bit()),
142            )
143            .field(
144                "core_1_area_pif_1_rd_rls",
145                &format_args!("{}", self.core_1_area_pif_1_rd_rls().bit()),
146            )
147            .field(
148                "core_1_area_pif_1_wr_rls",
149                &format_args!("{}", self.core_1_area_pif_1_wr_rls().bit()),
150            )
151            .field(
152                "core_1_sp_spill_min_rls",
153                &format_args!("{}", self.core_1_sp_spill_min_rls().bit()),
154            )
155            .field(
156                "core_1_sp_spill_max_rls",
157                &format_args!("{}", self.core_1_sp_spill_max_rls().bit()),
158            )
159            .field(
160                "core_1_iram0_exception_monitor_rls",
161                &format_args!("{}", self.core_1_iram0_exception_monitor_rls().bit()),
162            )
163            .field(
164                "core_1_dram0_exception_monitor_rls",
165                &format_args!("{}", self.core_1_dram0_exception_monitor_rls().bit()),
166            )
167            .finish()
168    }
169}
170#[cfg(feature = "impl-register-debug")]
171impl core::fmt::Debug for crate::generic::Reg<CORE_1_INTR_RLS_SPEC> {
172    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
173        core::fmt::Debug::fmt(&self.read(), f)
174    }
175}
176impl W {
177    #[doc = "Bit 0 - Core1 dram0 area0 read monitor interrupt enable"]
178    #[inline(always)]
179    #[must_use]
180    pub fn core_1_area_dram0_0_rd_rls(
181        &mut self,
182    ) -> CORE_1_AREA_DRAM0_0_RD_RLS_W<CORE_1_INTR_RLS_SPEC> {
183        CORE_1_AREA_DRAM0_0_RD_RLS_W::new(self, 0)
184    }
185    #[doc = "Bit 1 - Core1 dram0 area0 write monitor interrupt enable"]
186    #[inline(always)]
187    #[must_use]
188    pub fn core_1_area_dram0_0_wr_rls(
189        &mut self,
190    ) -> CORE_1_AREA_DRAM0_0_WR_RLS_W<CORE_1_INTR_RLS_SPEC> {
191        CORE_1_AREA_DRAM0_0_WR_RLS_W::new(self, 1)
192    }
193    #[doc = "Bit 2 - Core1 dram0 area1 read monitor interrupt enable"]
194    #[inline(always)]
195    #[must_use]
196    pub fn core_1_area_dram0_1_rd_rls(
197        &mut self,
198    ) -> CORE_1_AREA_DRAM0_1_RD_RLS_W<CORE_1_INTR_RLS_SPEC> {
199        CORE_1_AREA_DRAM0_1_RD_RLS_W::new(self, 2)
200    }
201    #[doc = "Bit 3 - Core1 dram0 area1 write monitor interrupt enable"]
202    #[inline(always)]
203    #[must_use]
204    pub fn core_1_area_dram0_1_wr_rls(
205        &mut self,
206    ) -> CORE_1_AREA_DRAM0_1_WR_RLS_W<CORE_1_INTR_RLS_SPEC> {
207        CORE_1_AREA_DRAM0_1_WR_RLS_W::new(self, 3)
208    }
209    #[doc = "Bit 4 - Core1 PIF area0 read monitor interrupt enable"]
210    #[inline(always)]
211    #[must_use]
212    pub fn core_1_area_pif_0_rd_rls(&mut self) -> CORE_1_AREA_PIF_0_RD_RLS_W<CORE_1_INTR_RLS_SPEC> {
213        CORE_1_AREA_PIF_0_RD_RLS_W::new(self, 4)
214    }
215    #[doc = "Bit 5 - Core1 PIF area0 write monitor interrupt enable"]
216    #[inline(always)]
217    #[must_use]
218    pub fn core_1_area_pif_0_wr_rls(&mut self) -> CORE_1_AREA_PIF_0_WR_RLS_W<CORE_1_INTR_RLS_SPEC> {
219        CORE_1_AREA_PIF_0_WR_RLS_W::new(self, 5)
220    }
221    #[doc = "Bit 6 - Core1 PIF area1 read monitor interrupt enable"]
222    #[inline(always)]
223    #[must_use]
224    pub fn core_1_area_pif_1_rd_rls(&mut self) -> CORE_1_AREA_PIF_1_RD_RLS_W<CORE_1_INTR_RLS_SPEC> {
225        CORE_1_AREA_PIF_1_RD_RLS_W::new(self, 6)
226    }
227    #[doc = "Bit 7 - Core1 PIF area1 write monitor interrupt enable"]
228    #[inline(always)]
229    #[must_use]
230    pub fn core_1_area_pif_1_wr_rls(&mut self) -> CORE_1_AREA_PIF_1_WR_RLS_W<CORE_1_INTR_RLS_SPEC> {
231        CORE_1_AREA_PIF_1_WR_RLS_W::new(self, 7)
232    }
233    #[doc = "Bit 8 - Core1 stackpoint underflow monitor interrupt enable"]
234    #[inline(always)]
235    #[must_use]
236    pub fn core_1_sp_spill_min_rls(&mut self) -> CORE_1_SP_SPILL_MIN_RLS_W<CORE_1_INTR_RLS_SPEC> {
237        CORE_1_SP_SPILL_MIN_RLS_W::new(self, 8)
238    }
239    #[doc = "Bit 9 - Core1 stackpoint overflow monitor interrupt enable"]
240    #[inline(always)]
241    #[must_use]
242    pub fn core_1_sp_spill_max_rls(&mut self) -> CORE_1_SP_SPILL_MAX_RLS_W<CORE_1_INTR_RLS_SPEC> {
243        CORE_1_SP_SPILL_MAX_RLS_W::new(self, 9)
244    }
245    #[doc = "Bit 10 - IBUS busy monitor interrupt enable"]
246    #[inline(always)]
247    #[must_use]
248    pub fn core_1_iram0_exception_monitor_rls(
249        &mut self,
250    ) -> CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_W<CORE_1_INTR_RLS_SPEC> {
251        CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_W::new(self, 10)
252    }
253    #[doc = "Bit 11 - DBUS busy monitor interrupt enbale"]
254    #[inline(always)]
255    #[must_use]
256    pub fn core_1_dram0_exception_monitor_rls(
257        &mut self,
258    ) -> CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_W<CORE_1_INTR_RLS_SPEC> {
259        CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_W::new(self, 11)
260    }
261}
262#[doc = "core1 monitor interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_intr_rls::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_intr_rls::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
263pub struct CORE_1_INTR_RLS_SPEC;
264impl crate::RegisterSpec for CORE_1_INTR_RLS_SPEC {
265    type Ux = u32;
266}
267#[doc = "`read()` method returns [`core_1_intr_rls::R`](R) reader structure"]
268impl crate::Readable for CORE_1_INTR_RLS_SPEC {}
269#[doc = "`write(|w| ..)` method takes [`core_1_intr_rls::W`](W) writer structure"]
270impl crate::Writable for CORE_1_INTR_RLS_SPEC {
271    type Safety = crate::Unsafe;
272    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
273    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
274}
275#[doc = "`reset()` method sets CORE_1_INTR_RLS to value 0"]
276impl crate::Resettable for CORE_1_INTR_RLS_SPEC {
277    const RESET_VALUE: u32 = 0;
278}
esp32p4/assist_debug/core_1_intr_rls.rs

esp32p4/assist_debug/
core_1_intr_rls.rs
