esp32p4/twai0/
clock_divider.rs

1#[doc = "Register `CLOCK_DIVIDER` reader"]
2pub type R = crate::R<CLOCK_DIVIDER_SPEC>;
3#[doc = "Register `CLOCK_DIVIDER` writer"]
4pub type W = crate::W<CLOCK_DIVIDER_SPEC>;
5#[doc = "Field `CD` reader - These bits are used to define the frequency at the external CLKOUT pin."]
6pub type CD_R = crate::FieldReader;
7#[doc = "Field `CD` writer - These bits are used to define the frequency at the external CLKOUT pin."]
8pub type CD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `CLOCK_OFF` reader - 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has R/W permission in reset mode and RO in operation mode."]
10pub type CLOCK_OFF_R = crate::BitReader;
11#[doc = "Field `CLOCK_OFF` writer - 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has R/W permission in reset mode and RO in operation mode."]
12pub type CLOCK_OFF_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    #[doc = "Bits 0:7 - These bits are used to define the frequency at the external CLKOUT pin."]
15    #[inline(always)]
16    pub fn cd(&self) -> CD_R {
17        CD_R::new((self.bits & 0xff) as u8)
18    }
19    #[doc = "Bit 8 - 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has R/W permission in reset mode and RO in operation mode."]
20    #[inline(always)]
21    pub fn clock_off(&self) -> CLOCK_OFF_R {
22        CLOCK_OFF_R::new(((self.bits >> 8) & 1) != 0)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("CLOCK_DIVIDER")
29            .field("cd", &format_args!("{}", self.cd().bits()))
30            .field("clock_off", &format_args!("{}", self.clock_off().bit()))
31            .finish()
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for crate::generic::Reg<CLOCK_DIVIDER_SPEC> {
36    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
37        core::fmt::Debug::fmt(&self.read(), f)
38    }
39}
40impl W {
41    #[doc = "Bits 0:7 - These bits are used to define the frequency at the external CLKOUT pin."]
42    #[inline(always)]
43    #[must_use]
44    pub fn cd(&mut self) -> CD_W<CLOCK_DIVIDER_SPEC> {
45        CD_W::new(self, 0)
46    }
47    #[doc = "Bit 8 - 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has R/W permission in reset mode and RO in operation mode."]
48    #[inline(always)]
49    #[must_use]
50    pub fn clock_off(&mut self) -> CLOCK_OFF_W<CLOCK_DIVIDER_SPEC> {
51        CLOCK_OFF_W::new(self, 8)
52    }
53}
54#[doc = "Clock divider register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_divider::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_divider::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
55pub struct CLOCK_DIVIDER_SPEC;
56impl crate::RegisterSpec for CLOCK_DIVIDER_SPEC {
57    type Ux = u32;
58}
59#[doc = "`read()` method returns [`clock_divider::R`](R) reader structure"]
60impl crate::Readable for CLOCK_DIVIDER_SPEC {}
61#[doc = "`write(|w| ..)` method takes [`clock_divider::W`](W) writer structure"]
62impl crate::Writable for CLOCK_DIVIDER_SPEC {
63    type Safety = crate::Unsafe;
64    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
65    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
66}
67#[doc = "`reset()` method sets CLOCK_DIVIDER to value 0"]
68impl crate::Resettable for CLOCK_DIVIDER_SPEC {
69    const RESET_VALUE: u32 = 0;
70}
esp32p4/twai0/clock_divider.rs

esp32p4/twai0/
clock_divider.rs
