esp32p4/timg0/
int_raw_timers.rs

1#[doc = "Register `INT_RAW_TIMERS` reader"]
2pub type R = crate::R<INT_RAW_TIMERS_SPEC>;
3#[doc = "Field `T(0-1)` reader - The raw interrupt status bit for the TIMG_T%s_INT interrupt."]
4pub type T_R = crate::BitReader;
5#[doc = "Field `WDT` reader - The raw interrupt status bit for the TIMG_WDT_INT interrupt."]
6pub type WDT_R = crate::BitReader;
7impl R {
8    #[doc = "The raw interrupt status bit for the TIMG_T(0-1)_INT interrupt."]
9    #[doc = ""]
10    #[doc = "NOTE: `n` is number of field in register. `n == 0` corresponds to `T0` field"]
11    #[inline(always)]
12    pub fn t(&self, n: u8) -> T_R {
13        #[allow(clippy::no_effect)]
14        [(); 2][n as usize];
15        T_R::new(((self.bits >> n) & 1) != 0)
16    }
17    #[doc = "Iterator for array of:"]
18    #[doc = "The raw interrupt status bit for the TIMG_T(0-1)_INT interrupt."]
19    #[inline(always)]
20    pub fn t_iter(&self) -> impl Iterator<Item = T_R> + '_ {
21        (0..2).map(move |n| T_R::new(((self.bits >> n) & 1) != 0))
22    }
23    #[doc = "Bit 0 - The raw interrupt status bit for the TIMG_T0_INT interrupt."]
24    #[inline(always)]
25    pub fn t0(&self) -> T_R {
26        T_R::new((self.bits & 1) != 0)
27    }
28    #[doc = "Bit 1 - The raw interrupt status bit for the TIMG_T1_INT interrupt."]
29    #[inline(always)]
30    pub fn t1(&self) -> T_R {
31        T_R::new(((self.bits >> 1) & 1) != 0)
32    }
33    #[doc = "Bit 2 - The raw interrupt status bit for the TIMG_WDT_INT interrupt."]
34    #[inline(always)]
35    pub fn wdt(&self) -> WDT_R {
36        WDT_R::new(((self.bits >> 2) & 1) != 0)
37    }
38}
39#[cfg(feature = "impl-register-debug")]
40impl core::fmt::Debug for R {
41    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
42        f.debug_struct("INT_RAW_TIMERS")
43            .field("t0", &format_args!("{}", self.t0().bit()))
44            .field("t1", &format_args!("{}", self.t1().bit()))
45            .field("wdt", &format_args!("{}", self.wdt().bit()))
46            .finish()
47    }
48}
49#[cfg(feature = "impl-register-debug")]
50impl core::fmt::Debug for crate::generic::Reg<INT_RAW_TIMERS_SPEC> {
51    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
52        core::fmt::Debug::fmt(&self.read(), f)
53    }
54}
55#[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw_timers::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
56pub struct INT_RAW_TIMERS_SPEC;
57impl crate::RegisterSpec for INT_RAW_TIMERS_SPEC {
58    type Ux = u32;
59}
60#[doc = "`read()` method returns [`int_raw_timers::R`](R) reader structure"]
61impl crate::Readable for INT_RAW_TIMERS_SPEC {}
62#[doc = "`reset()` method sets INT_RAW_TIMERS to value 0"]
63impl crate::Resettable for INT_RAW_TIMERS_SPEC {
64    const RESET_VALUE: u32 = 0;
65}
esp32p4/timg0/int_raw_timers.rs

esp32p4/timg0/
int_raw_timers.rs
