esp32p4/systimer/
int_st.rs1#[doc = "Register `INT_ST` reader"]
2pub type R = crate::R<INT_ST_SPEC>;
3#[doc = "Field `TARGET0` reader - interupt0 status"]
4pub type TARGET0_R = crate::BitReader;
5#[doc = "Field `TARGET1` reader - interupt1 status"]
6pub type TARGET1_R = crate::BitReader;
7#[doc = "Field `TARGET2` reader - interupt2 status"]
8pub type TARGET2_R = crate::BitReader;
9impl R {
10 #[doc = "Bit 0 - interupt0 status"]
11 #[inline(always)]
12 pub fn target0(&self) -> TARGET0_R {
13 TARGET0_R::new((self.bits & 1) != 0)
14 }
15 #[doc = "Bit 1 - interupt1 status"]
16 #[inline(always)]
17 pub fn target1(&self) -> TARGET1_R {
18 TARGET1_R::new(((self.bits >> 1) & 1) != 0)
19 }
20 #[doc = "Bit 2 - interupt2 status"]
21 #[inline(always)]
22 pub fn target2(&self) -> TARGET2_R {
23 TARGET2_R::new(((self.bits >> 2) & 1) != 0)
24 }
25}
26#[cfg(feature = "impl-register-debug")]
27impl core::fmt::Debug for R {
28 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
29 f.debug_struct("INT_ST")
30 .field("target0", &format_args!("{}", self.target0().bit()))
31 .field("target1", &format_args!("{}", self.target1().bit()))
32 .field("target2", &format_args!("{}", self.target2().bit()))
33 .finish()
34 }
35}
36#[cfg(feature = "impl-register-debug")]
37impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
38 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
39 core::fmt::Debug::fmt(&self.read(), f)
40 }
41}
42#[doc = "systimer interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
43pub struct INT_ST_SPEC;
44impl crate::RegisterSpec for INT_ST_SPEC {
45 type Ux = u32;
46}
47#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
48impl crate::Readable for INT_ST_SPEC {}
49#[doc = "`reset()` method sets INT_ST to value 0"]
50impl crate::Resettable for INT_ST_SPEC {
51 const RESET_VALUE: u32 = 0;
52}