1#[doc = "Register `USER` reader"]
2pub type R = crate::R<USER_SPEC>;
3#[doc = "Register `USER` writer"]
4pub type W = crate::W<USER_SPEC>;
5#[doc = "Field `DOUTDIN` reader - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
6pub type DOUTDIN_R = crate::BitReader;
7#[doc = "Field `DOUTDIN` writer - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
8pub type DOUTDIN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `QPI_MODE` reader - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."]
10pub type QPI_MODE_R = crate::BitReader;
11#[doc = "Field `QPI_MODE` writer - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."]
12pub type QPI_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `TSCK_I_EDGE` reader - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."]
14pub type TSCK_I_EDGE_R = crate::BitReader;
15#[doc = "Field `TSCK_I_EDGE` writer - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."]
16pub type TSCK_I_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CS_HOLD` reader - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."]
18pub type CS_HOLD_R = crate::BitReader;
19#[doc = "Field `CS_HOLD` writer - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."]
20pub type CS_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CS_SETUP` reader - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."]
22pub type CS_SETUP_R = crate::BitReader;
23#[doc = "Field `CS_SETUP` writer - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."]
24pub type CS_SETUP_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `RSCK_I_EDGE` reader - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."]
26pub type RSCK_I_EDGE_R = crate::BitReader;
27#[doc = "Field `RSCK_I_EDGE` writer - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."]
28pub type RSCK_I_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `CK_OUT_EDGE` reader - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state."]
30pub type CK_OUT_EDGE_R = crate::BitReader;
31#[doc = "Field `CK_OUT_EDGE` writer - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state."]
32pub type CK_OUT_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `FWRITE_DUAL` reader - In the write operations read-data phase apply 2 signals. Can be configured in CONF state."]
34pub type FWRITE_DUAL_R = crate::BitReader;
35#[doc = "Field `FWRITE_DUAL` writer - In the write operations read-data phase apply 2 signals. Can be configured in CONF state."]
36pub type FWRITE_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `FWRITE_QUAD` reader - In the write operations read-data phase apply 4 signals. Can be configured in CONF state."]
38pub type FWRITE_QUAD_R = crate::BitReader;
39#[doc = "Field `FWRITE_QUAD` writer - In the write operations read-data phase apply 4 signals. Can be configured in CONF state."]
40pub type FWRITE_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `SIO` reader - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."]
42pub type SIO_R = crate::BitReader;
43#[doc = "Field `SIO` writer - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."]
44pub type SIO_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `USR_MISO_HIGHPART` reader - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
46pub type USR_MISO_HIGHPART_R = crate::BitReader;
47#[doc = "Field `USR_MISO_HIGHPART` writer - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
48pub type USR_MISO_HIGHPART_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `USR_MOSI_HIGHPART` reader - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
50pub type USR_MOSI_HIGHPART_R = crate::BitReader;
51#[doc = "Field `USR_MOSI_HIGHPART` writer - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
52pub type USR_MOSI_HIGHPART_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `USR_DUMMY_IDLE` reader - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."]
54pub type USR_DUMMY_IDLE_R = crate::BitReader;
55#[doc = "Field `USR_DUMMY_IDLE` writer - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."]
56pub type USR_DUMMY_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `USR_MOSI` reader - This bit enable the write-data phase of an operation. Can be configured in CONF state."]
58pub type USR_MOSI_R = crate::BitReader;
59#[doc = "Field `USR_MOSI` writer - This bit enable the write-data phase of an operation. Can be configured in CONF state."]
60pub type USR_MOSI_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `USR_MISO` reader - This bit enable the read-data phase of an operation. Can be configured in CONF state."]
62pub type USR_MISO_R = crate::BitReader;
63#[doc = "Field `USR_MISO` writer - This bit enable the read-data phase of an operation. Can be configured in CONF state."]
64pub type USR_MISO_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `USR_DUMMY` reader - This bit enable the dummy phase of an operation. Can be configured in CONF state."]
66pub type USR_DUMMY_R = crate::BitReader;
67#[doc = "Field `USR_DUMMY` writer - This bit enable the dummy phase of an operation. Can be configured in CONF state."]
68pub type USR_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `USR_ADDR` reader - This bit enable the address phase of an operation. Can be configured in CONF state."]
70pub type USR_ADDR_R = crate::BitReader;
71#[doc = "Field `USR_ADDR` writer - This bit enable the address phase of an operation. Can be configured in CONF state."]
72pub type USR_ADDR_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `USR_COMMAND` reader - This bit enable the command phase of an operation. Can be configured in CONF state."]
74pub type USR_COMMAND_R = crate::BitReader;
75#[doc = "Field `USR_COMMAND` writer - This bit enable the command phase of an operation. Can be configured in CONF state."]
76pub type USR_COMMAND_W<'a, REG> = crate::BitWriter<'a, REG>;
77impl R {
78 #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
79 #[inline(always)]
80 pub fn doutdin(&self) -> DOUTDIN_R {
81 DOUTDIN_R::new((self.bits & 1) != 0)
82 }
83 #[doc = "Bit 3 - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."]
84 #[inline(always)]
85 pub fn qpi_mode(&self) -> QPI_MODE_R {
86 QPI_MODE_R::new(((self.bits >> 3) & 1) != 0)
87 }
88 #[doc = "Bit 5 - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."]
89 #[inline(always)]
90 pub fn tsck_i_edge(&self) -> TSCK_I_EDGE_R {
91 TSCK_I_EDGE_R::new(((self.bits >> 5) & 1) != 0)
92 }
93 #[doc = "Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."]
94 #[inline(always)]
95 pub fn cs_hold(&self) -> CS_HOLD_R {
96 CS_HOLD_R::new(((self.bits >> 6) & 1) != 0)
97 }
98 #[doc = "Bit 7 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."]
99 #[inline(always)]
100 pub fn cs_setup(&self) -> CS_SETUP_R {
101 CS_SETUP_R::new(((self.bits >> 7) & 1) != 0)
102 }
103 #[doc = "Bit 8 - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."]
104 #[inline(always)]
105 pub fn rsck_i_edge(&self) -> RSCK_I_EDGE_R {
106 RSCK_I_EDGE_R::new(((self.bits >> 8) & 1) != 0)
107 }
108 #[doc = "Bit 9 - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state."]
109 #[inline(always)]
110 pub fn ck_out_edge(&self) -> CK_OUT_EDGE_R {
111 CK_OUT_EDGE_R::new(((self.bits >> 9) & 1) != 0)
112 }
113 #[doc = "Bit 12 - In the write operations read-data phase apply 2 signals. Can be configured in CONF state."]
114 #[inline(always)]
115 pub fn fwrite_dual(&self) -> FWRITE_DUAL_R {
116 FWRITE_DUAL_R::new(((self.bits >> 12) & 1) != 0)
117 }
118 #[doc = "Bit 13 - In the write operations read-data phase apply 4 signals. Can be configured in CONF state."]
119 #[inline(always)]
120 pub fn fwrite_quad(&self) -> FWRITE_QUAD_R {
121 FWRITE_QUAD_R::new(((self.bits >> 13) & 1) != 0)
122 }
123 #[doc = "Bit 17 - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."]
124 #[inline(always)]
125 pub fn sio(&self) -> SIO_R {
126 SIO_R::new(((self.bits >> 17) & 1) != 0)
127 }
128 #[doc = "Bit 24 - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
129 #[inline(always)]
130 pub fn usr_miso_highpart(&self) -> USR_MISO_HIGHPART_R {
131 USR_MISO_HIGHPART_R::new(((self.bits >> 24) & 1) != 0)
132 }
133 #[doc = "Bit 25 - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
134 #[inline(always)]
135 pub fn usr_mosi_highpart(&self) -> USR_MOSI_HIGHPART_R {
136 USR_MOSI_HIGHPART_R::new(((self.bits >> 25) & 1) != 0)
137 }
138 #[doc = "Bit 26 - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."]
139 #[inline(always)]
140 pub fn usr_dummy_idle(&self) -> USR_DUMMY_IDLE_R {
141 USR_DUMMY_IDLE_R::new(((self.bits >> 26) & 1) != 0)
142 }
143 #[doc = "Bit 27 - This bit enable the write-data phase of an operation. Can be configured in CONF state."]
144 #[inline(always)]
145 pub fn usr_mosi(&self) -> USR_MOSI_R {
146 USR_MOSI_R::new(((self.bits >> 27) & 1) != 0)
147 }
148 #[doc = "Bit 28 - This bit enable the read-data phase of an operation. Can be configured in CONF state."]
149 #[inline(always)]
150 pub fn usr_miso(&self) -> USR_MISO_R {
151 USR_MISO_R::new(((self.bits >> 28) & 1) != 0)
152 }
153 #[doc = "Bit 29 - This bit enable the dummy phase of an operation. Can be configured in CONF state."]
154 #[inline(always)]
155 pub fn usr_dummy(&self) -> USR_DUMMY_R {
156 USR_DUMMY_R::new(((self.bits >> 29) & 1) != 0)
157 }
158 #[doc = "Bit 30 - This bit enable the address phase of an operation. Can be configured in CONF state."]
159 #[inline(always)]
160 pub fn usr_addr(&self) -> USR_ADDR_R {
161 USR_ADDR_R::new(((self.bits >> 30) & 1) != 0)
162 }
163 #[doc = "Bit 31 - This bit enable the command phase of an operation. Can be configured in CONF state."]
164 #[inline(always)]
165 pub fn usr_command(&self) -> USR_COMMAND_R {
166 USR_COMMAND_R::new(((self.bits >> 31) & 1) != 0)
167 }
168}
169#[cfg(feature = "impl-register-debug")]
170impl core::fmt::Debug for R {
171 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
172 f.debug_struct("USER")
173 .field("doutdin", &format_args!("{}", self.doutdin().bit()))
174 .field("qpi_mode", &format_args!("{}", self.qpi_mode().bit()))
175 .field("tsck_i_edge", &format_args!("{}", self.tsck_i_edge().bit()))
176 .field("cs_hold", &format_args!("{}", self.cs_hold().bit()))
177 .field("cs_setup", &format_args!("{}", self.cs_setup().bit()))
178 .field("rsck_i_edge", &format_args!("{}", self.rsck_i_edge().bit()))
179 .field("ck_out_edge", &format_args!("{}", self.ck_out_edge().bit()))
180 .field("fwrite_dual", &format_args!("{}", self.fwrite_dual().bit()))
181 .field("fwrite_quad", &format_args!("{}", self.fwrite_quad().bit()))
182 .field("sio", &format_args!("{}", self.sio().bit()))
183 .field(
184 "usr_miso_highpart",
185 &format_args!("{}", self.usr_miso_highpart().bit()),
186 )
187 .field(
188 "usr_mosi_highpart",
189 &format_args!("{}", self.usr_mosi_highpart().bit()),
190 )
191 .field(
192 "usr_dummy_idle",
193 &format_args!("{}", self.usr_dummy_idle().bit()),
194 )
195 .field("usr_mosi", &format_args!("{}", self.usr_mosi().bit()))
196 .field("usr_miso", &format_args!("{}", self.usr_miso().bit()))
197 .field("usr_dummy", &format_args!("{}", self.usr_dummy().bit()))
198 .field("usr_addr", &format_args!("{}", self.usr_addr().bit()))
199 .field("usr_command", &format_args!("{}", self.usr_command().bit()))
200 .finish()
201 }
202}
203#[cfg(feature = "impl-register-debug")]
204impl core::fmt::Debug for crate::generic::Reg<USER_SPEC> {
205 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
206 core::fmt::Debug::fmt(&self.read(), f)
207 }
208}
209impl W {
210 #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
211 #[inline(always)]
212 #[must_use]
213 pub fn doutdin(&mut self) -> DOUTDIN_W<USER_SPEC> {
214 DOUTDIN_W::new(self, 0)
215 }
216 #[doc = "Bit 3 - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."]
217 #[inline(always)]
218 #[must_use]
219 pub fn qpi_mode(&mut self) -> QPI_MODE_W<USER_SPEC> {
220 QPI_MODE_W::new(self, 3)
221 }
222 #[doc = "Bit 5 - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."]
223 #[inline(always)]
224 #[must_use]
225 pub fn tsck_i_edge(&mut self) -> TSCK_I_EDGE_W<USER_SPEC> {
226 TSCK_I_EDGE_W::new(self, 5)
227 }
228 #[doc = "Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."]
229 #[inline(always)]
230 #[must_use]
231 pub fn cs_hold(&mut self) -> CS_HOLD_W<USER_SPEC> {
232 CS_HOLD_W::new(self, 6)
233 }
234 #[doc = "Bit 7 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."]
235 #[inline(always)]
236 #[must_use]
237 pub fn cs_setup(&mut self) -> CS_SETUP_W<USER_SPEC> {
238 CS_SETUP_W::new(self, 7)
239 }
240 #[doc = "Bit 8 - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."]
241 #[inline(always)]
242 #[must_use]
243 pub fn rsck_i_edge(&mut self) -> RSCK_I_EDGE_W<USER_SPEC> {
244 RSCK_I_EDGE_W::new(self, 8)
245 }
246 #[doc = "Bit 9 - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state."]
247 #[inline(always)]
248 #[must_use]
249 pub fn ck_out_edge(&mut self) -> CK_OUT_EDGE_W<USER_SPEC> {
250 CK_OUT_EDGE_W::new(self, 9)
251 }
252 #[doc = "Bit 12 - In the write operations read-data phase apply 2 signals. Can be configured in CONF state."]
253 #[inline(always)]
254 #[must_use]
255 pub fn fwrite_dual(&mut self) -> FWRITE_DUAL_W<USER_SPEC> {
256 FWRITE_DUAL_W::new(self, 12)
257 }
258 #[doc = "Bit 13 - In the write operations read-data phase apply 4 signals. Can be configured in CONF state."]
259 #[inline(always)]
260 #[must_use]
261 pub fn fwrite_quad(&mut self) -> FWRITE_QUAD_W<USER_SPEC> {
262 FWRITE_QUAD_W::new(self, 13)
263 }
264 #[doc = "Bit 17 - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."]
265 #[inline(always)]
266 #[must_use]
267 pub fn sio(&mut self) -> SIO_W<USER_SPEC> {
268 SIO_W::new(self, 17)
269 }
270 #[doc = "Bit 24 - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
271 #[inline(always)]
272 #[must_use]
273 pub fn usr_miso_highpart(&mut self) -> USR_MISO_HIGHPART_W<USER_SPEC> {
274 USR_MISO_HIGHPART_W::new(self, 24)
275 }
276 #[doc = "Bit 25 - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
277 #[inline(always)]
278 #[must_use]
279 pub fn usr_mosi_highpart(&mut self) -> USR_MOSI_HIGHPART_W<USER_SPEC> {
280 USR_MOSI_HIGHPART_W::new(self, 25)
281 }
282 #[doc = "Bit 26 - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."]
283 #[inline(always)]
284 #[must_use]
285 pub fn usr_dummy_idle(&mut self) -> USR_DUMMY_IDLE_W<USER_SPEC> {
286 USR_DUMMY_IDLE_W::new(self, 26)
287 }
288 #[doc = "Bit 27 - This bit enable the write-data phase of an operation. Can be configured in CONF state."]
289 #[inline(always)]
290 #[must_use]
291 pub fn usr_mosi(&mut self) -> USR_MOSI_W<USER_SPEC> {
292 USR_MOSI_W::new(self, 27)
293 }
294 #[doc = "Bit 28 - This bit enable the read-data phase of an operation. Can be configured in CONF state."]
295 #[inline(always)]
296 #[must_use]
297 pub fn usr_miso(&mut self) -> USR_MISO_W<USER_SPEC> {
298 USR_MISO_W::new(self, 28)
299 }
300 #[doc = "Bit 29 - This bit enable the dummy phase of an operation. Can be configured in CONF state."]
301 #[inline(always)]
302 #[must_use]
303 pub fn usr_dummy(&mut self) -> USR_DUMMY_W<USER_SPEC> {
304 USR_DUMMY_W::new(self, 29)
305 }
306 #[doc = "Bit 30 - This bit enable the address phase of an operation. Can be configured in CONF state."]
307 #[inline(always)]
308 #[must_use]
309 pub fn usr_addr(&mut self) -> USR_ADDR_W<USER_SPEC> {
310 USR_ADDR_W::new(self, 30)
311 }
312 #[doc = "Bit 31 - This bit enable the command phase of an operation. Can be configured in CONF state."]
313 #[inline(always)]
314 #[must_use]
315 pub fn usr_command(&mut self) -> USR_COMMAND_W<USER_SPEC> {
316 USR_COMMAND_W::new(self, 31)
317 }
318}
319#[doc = "SPI USER control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`user::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`user::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
320pub struct USER_SPEC;
321impl crate::RegisterSpec for USER_SPEC {
322 type Ux = u32;
323}
324#[doc = "`read()` method returns [`user::R`](R) reader structure"]
325impl crate::Readable for USER_SPEC {}
326#[doc = "`write(|w| ..)` method takes [`user::W`](W) writer structure"]
327impl crate::Writable for USER_SPEC {
328 type Safety = crate::Unsafe;
329 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
330 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
331}
332#[doc = "`reset()` method sets USER to value 0x8000_00c0"]
333impl crate::Resettable for USER_SPEC {
334 const RESET_VALUE: u32 = 0x8000_00c0;
335}