esp32p4/spi0/
timing_cali.rs

1#[doc = "Register `TIMING_CALI` reader"]
2pub type R = crate::R<TIMING_CALI_SPEC>;
3#[doc = "Register `TIMING_CALI` writer"]
4pub type W = crate::W<TIMING_CALI_SPEC>;
5#[doc = "Field `TIMING_CLK_ENA` reader - The bit is used to enable timing adjust clock for all reading operations."]
6pub type TIMING_CLK_ENA_R = crate::BitReader;
7#[doc = "Field `TIMING_CLK_ENA` writer - The bit is used to enable timing adjust clock for all reading operations."]
8pub type TIMING_CLK_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TIMING_CALI` reader - The bit is used to enable timing auto-calibration for all reading operations."]
10pub type TIMING_CALI_R = crate::BitReader;
11#[doc = "Field `TIMING_CALI` writer - The bit is used to enable timing auto-calibration for all reading operations."]
12pub type TIMING_CALI_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `EXTRA_DUMMY_CYCLELEN` reader - add extra dummy spi clock cycle length for spi clock calibration."]
14pub type EXTRA_DUMMY_CYCLELEN_R = crate::FieldReader;
15#[doc = "Field `EXTRA_DUMMY_CYCLELEN` writer - add extra dummy spi clock cycle length for spi clock calibration."]
16pub type EXTRA_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17#[doc = "Field `DLL_TIMING_CALI` reader - Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash."]
18pub type DLL_TIMING_CALI_R = crate::BitReader;
19#[doc = "Field `DLL_TIMING_CALI` writer - Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash."]
20pub type DLL_TIMING_CALI_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `UPDATE` writer - Set this bit to update delay mode, delay num and extra dummy in MSPI."]
22pub type UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>;
23impl R {
24    #[doc = "Bit 0 - The bit is used to enable timing adjust clock for all reading operations."]
25    #[inline(always)]
26    pub fn timing_clk_ena(&self) -> TIMING_CLK_ENA_R {
27        TIMING_CLK_ENA_R::new((self.bits & 1) != 0)
28    }
29    #[doc = "Bit 1 - The bit is used to enable timing auto-calibration for all reading operations."]
30    #[inline(always)]
31    pub fn timing_cali(&self) -> TIMING_CALI_R {
32        TIMING_CALI_R::new(((self.bits >> 1) & 1) != 0)
33    }
34    #[doc = "Bits 2:4 - add extra dummy spi clock cycle length for spi clock calibration."]
35    #[inline(always)]
36    pub fn extra_dummy_cyclelen(&self) -> EXTRA_DUMMY_CYCLELEN_R {
37        EXTRA_DUMMY_CYCLELEN_R::new(((self.bits >> 2) & 7) as u8)
38    }
39    #[doc = "Bit 5 - Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash."]
40    #[inline(always)]
41    pub fn dll_timing_cali(&self) -> DLL_TIMING_CALI_R {
42        DLL_TIMING_CALI_R::new(((self.bits >> 5) & 1) != 0)
43    }
44}
45#[cfg(feature = "impl-register-debug")]
46impl core::fmt::Debug for R {
47    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
48        f.debug_struct("TIMING_CALI")
49            .field(
50                "timing_clk_ena",
51                &format_args!("{}", self.timing_clk_ena().bit()),
52            )
53            .field("timing_cali", &format_args!("{}", self.timing_cali().bit()))
54            .field(
55                "extra_dummy_cyclelen",
56                &format_args!("{}", self.extra_dummy_cyclelen().bits()),
57            )
58            .field(
59                "dll_timing_cali",
60                &format_args!("{}", self.dll_timing_cali().bit()),
61            )
62            .finish()
63    }
64}
65#[cfg(feature = "impl-register-debug")]
66impl core::fmt::Debug for crate::generic::Reg<TIMING_CALI_SPEC> {
67    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
68        core::fmt::Debug::fmt(&self.read(), f)
69    }
70}
71impl W {
72    #[doc = "Bit 0 - The bit is used to enable timing adjust clock for all reading operations."]
73    #[inline(always)]
74    #[must_use]
75    pub fn timing_clk_ena(&mut self) -> TIMING_CLK_ENA_W<TIMING_CALI_SPEC> {
76        TIMING_CLK_ENA_W::new(self, 0)
77    }
78    #[doc = "Bit 1 - The bit is used to enable timing auto-calibration for all reading operations."]
79    #[inline(always)]
80    #[must_use]
81    pub fn timing_cali(&mut self) -> TIMING_CALI_W<TIMING_CALI_SPEC> {
82        TIMING_CALI_W::new(self, 1)
83    }
84    #[doc = "Bits 2:4 - add extra dummy spi clock cycle length for spi clock calibration."]
85    #[inline(always)]
86    #[must_use]
87    pub fn extra_dummy_cyclelen(&mut self) -> EXTRA_DUMMY_CYCLELEN_W<TIMING_CALI_SPEC> {
88        EXTRA_DUMMY_CYCLELEN_W::new(self, 2)
89    }
90    #[doc = "Bit 5 - Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash."]
91    #[inline(always)]
92    #[must_use]
93    pub fn dll_timing_cali(&mut self) -> DLL_TIMING_CALI_W<TIMING_CALI_SPEC> {
94        DLL_TIMING_CALI_W::new(self, 5)
95    }
96    #[doc = "Bit 6 - Set this bit to update delay mode, delay num and extra dummy in MSPI."]
97    #[inline(always)]
98    #[must_use]
99    pub fn update(&mut self) -> UPDATE_W<TIMING_CALI_SPEC> {
100        UPDATE_W::new(self, 6)
101    }
102}
103#[doc = "SPI0 flash timing calibration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timing_cali::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timing_cali::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
104pub struct TIMING_CALI_SPEC;
105impl crate::RegisterSpec for TIMING_CALI_SPEC {
106    type Ux = u32;
107}
108#[doc = "`read()` method returns [`timing_cali::R`](R) reader structure"]
109impl crate::Readable for TIMING_CALI_SPEC {}
110#[doc = "`write(|w| ..)` method takes [`timing_cali::W`](W) writer structure"]
111impl crate::Writable for TIMING_CALI_SPEC {
112    type Safety = crate::Unsafe;
113    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
114    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
115}
116#[doc = "`reset()` method sets TIMING_CALI to value 0x01"]
117impl crate::Resettable for TIMING_CALI_SPEC {
118    const RESET_VALUE: u32 = 0x01;
119}
esp32p4/spi0/timing_cali.rs

esp32p4/spi0/
timing_cali.rs
