1#[doc = "Register `SRAM_CMD` reader"]
2pub type R = crate::R<SRAM_CMD_SPEC>;
3#[doc = "Register `SRAM_CMD` writer"]
4pub type W = crate::W<SRAM_CMD_SPEC>;
5#[doc = "Field `SCLK_MODE` reader - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on."]
6pub type SCLK_MODE_R = crate::FieldReader;
7#[doc = "Field `SCLK_MODE` writer - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on."]
8pub type SCLK_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `SWB_MODE` reader - Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit."]
10pub type SWB_MODE_R = crate::FieldReader;
11#[doc = "Field `SWB_MODE` writer - Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit."]
12pub type SWB_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13#[doc = "Field `SDIN_DUAL` reader - For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."]
14pub type SDIN_DUAL_R = crate::BitReader;
15#[doc = "Field `SDIN_DUAL` writer - For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."]
16pub type SDIN_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SDOUT_DUAL` reader - For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."]
18pub type SDOUT_DUAL_R = crate::BitReader;
19#[doc = "Field `SDOUT_DUAL` writer - For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."]
20pub type SDOUT_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `SADDR_DUAL` reader - For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."]
22pub type SADDR_DUAL_R = crate::BitReader;
23#[doc = "Field `SADDR_DUAL` writer - For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."]
24pub type SADDR_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SDIN_QUAD` reader - For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
26pub type SDIN_QUAD_R = crate::BitReader;
27#[doc = "Field `SDIN_QUAD` writer - For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
28pub type SDIN_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `SDOUT_QUAD` reader - For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
30pub type SDOUT_QUAD_R = crate::BitReader;
31#[doc = "Field `SDOUT_QUAD` writer - For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
32pub type SDOUT_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `SADDR_QUAD` reader - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
34pub type SADDR_QUAD_R = crate::BitReader;
35#[doc = "Field `SADDR_QUAD` writer - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
36pub type SADDR_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `SCMD_QUAD` reader - For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
38pub type SCMD_QUAD_R = crate::BitReader;
39#[doc = "Field `SCMD_QUAD` writer - For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
40pub type SCMD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `SDIN_OCT` reader - For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable."]
42pub type SDIN_OCT_R = crate::BitReader;
43#[doc = "Field `SDIN_OCT` writer - For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable."]
44pub type SDIN_OCT_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `SDOUT_OCT` reader - For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable."]
46pub type SDOUT_OCT_R = crate::BitReader;
47#[doc = "Field `SDOUT_OCT` writer - For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable."]
48pub type SDOUT_OCT_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `SADDR_OCT` reader - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable."]
50pub type SADDR_OCT_R = crate::BitReader;
51#[doc = "Field `SADDR_OCT` writer - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable."]
52pub type SADDR_OCT_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `SCMD_OCT` reader - For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable."]
54pub type SCMD_OCT_R = crate::BitReader;
55#[doc = "Field `SCMD_OCT` writer - For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable."]
56pub type SCMD_OCT_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `SDUMMY_RIN` reader - In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."]
58pub type SDUMMY_RIN_R = crate::BitReader;
59#[doc = "Field `SDUMMY_RIN` writer - In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."]
60pub type SDUMMY_RIN_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `SDUMMY_WOUT` reader - In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."]
62pub type SDUMMY_WOUT_R = crate::BitReader;
63#[doc = "Field `SDUMMY_WOUT` writer - In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."]
64pub type SDUMMY_WOUT_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT` reader - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller."]
66pub type SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_R = crate::BitReader;
67#[doc = "Field `SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT` writer - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller."]
68pub type SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `SPI_SMEM_WDUMMY_ALWAYS_OUT` reader - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO\\[7:0\\] is output by the MSPI controller."]
70pub type SPI_SMEM_WDUMMY_ALWAYS_OUT_R = crate::BitReader;
71#[doc = "Field `SPI_SMEM_WDUMMY_ALWAYS_OUT` writer - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO\\[7:0\\] is output by the MSPI controller."]
72pub type SPI_SMEM_WDUMMY_ALWAYS_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `SDIN_HEX` reader - For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable."]
74pub type SDIN_HEX_R = crate::BitReader;
75#[doc = "Field `SDIN_HEX` writer - For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable."]
76pub type SDIN_HEX_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `SDOUT_HEX` reader - For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable."]
78pub type SDOUT_HEX_R = crate::BitReader;
79#[doc = "Field `SDOUT_HEX` writer - For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable."]
80pub type SDOUT_HEX_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `SPI_SMEM_DQS_IE_ALWAYS_ON` reader - When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others."]
82pub type SPI_SMEM_DQS_IE_ALWAYS_ON_R = crate::BitReader;
83#[doc = "Field `SPI_SMEM_DQS_IE_ALWAYS_ON` writer - When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others."]
84pub type SPI_SMEM_DQS_IE_ALWAYS_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `SPI_SMEM_DATA_IE_ALWAYS_ON` reader - When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO\\[7:0\\] are always 1. 0: Others."]
86pub type SPI_SMEM_DATA_IE_ALWAYS_ON_R = crate::BitReader;
87#[doc = "Field `SPI_SMEM_DATA_IE_ALWAYS_ON` writer - When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO\\[7:0\\] are always 1. 0: Others."]
88pub type SPI_SMEM_DATA_IE_ALWAYS_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
89impl R {
90 #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on."]
91 #[inline(always)]
92 pub fn sclk_mode(&self) -> SCLK_MODE_R {
93 SCLK_MODE_R::new((self.bits & 3) as u8)
94 }
95 #[doc = "Bits 2:9 - Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit."]
96 #[inline(always)]
97 pub fn swb_mode(&self) -> SWB_MODE_R {
98 SWB_MODE_R::new(((self.bits >> 2) & 0xff) as u8)
99 }
100 #[doc = "Bit 10 - For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."]
101 #[inline(always)]
102 pub fn sdin_dual(&self) -> SDIN_DUAL_R {
103 SDIN_DUAL_R::new(((self.bits >> 10) & 1) != 0)
104 }
105 #[doc = "Bit 11 - For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."]
106 #[inline(always)]
107 pub fn sdout_dual(&self) -> SDOUT_DUAL_R {
108 SDOUT_DUAL_R::new(((self.bits >> 11) & 1) != 0)
109 }
110 #[doc = "Bit 12 - For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."]
111 #[inline(always)]
112 pub fn saddr_dual(&self) -> SADDR_DUAL_R {
113 SADDR_DUAL_R::new(((self.bits >> 12) & 1) != 0)
114 }
115 #[doc = "Bit 14 - For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
116 #[inline(always)]
117 pub fn sdin_quad(&self) -> SDIN_QUAD_R {
118 SDIN_QUAD_R::new(((self.bits >> 14) & 1) != 0)
119 }
120 #[doc = "Bit 15 - For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
121 #[inline(always)]
122 pub fn sdout_quad(&self) -> SDOUT_QUAD_R {
123 SDOUT_QUAD_R::new(((self.bits >> 15) & 1) != 0)
124 }
125 #[doc = "Bit 16 - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
126 #[inline(always)]
127 pub fn saddr_quad(&self) -> SADDR_QUAD_R {
128 SADDR_QUAD_R::new(((self.bits >> 16) & 1) != 0)
129 }
130 #[doc = "Bit 17 - For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
131 #[inline(always)]
132 pub fn scmd_quad(&self) -> SCMD_QUAD_R {
133 SCMD_QUAD_R::new(((self.bits >> 17) & 1) != 0)
134 }
135 #[doc = "Bit 18 - For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable."]
136 #[inline(always)]
137 pub fn sdin_oct(&self) -> SDIN_OCT_R {
138 SDIN_OCT_R::new(((self.bits >> 18) & 1) != 0)
139 }
140 #[doc = "Bit 19 - For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable."]
141 #[inline(always)]
142 pub fn sdout_oct(&self) -> SDOUT_OCT_R {
143 SDOUT_OCT_R::new(((self.bits >> 19) & 1) != 0)
144 }
145 #[doc = "Bit 20 - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable."]
146 #[inline(always)]
147 pub fn saddr_oct(&self) -> SADDR_OCT_R {
148 SADDR_OCT_R::new(((self.bits >> 20) & 1) != 0)
149 }
150 #[doc = "Bit 21 - For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable."]
151 #[inline(always)]
152 pub fn scmd_oct(&self) -> SCMD_OCT_R {
153 SCMD_OCT_R::new(((self.bits >> 21) & 1) != 0)
154 }
155 #[doc = "Bit 22 - In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."]
156 #[inline(always)]
157 pub fn sdummy_rin(&self) -> SDUMMY_RIN_R {
158 SDUMMY_RIN_R::new(((self.bits >> 22) & 1) != 0)
159 }
160 #[doc = "Bit 23 - In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."]
161 #[inline(always)]
162 pub fn sdummy_wout(&self) -> SDUMMY_WOUT_R {
163 SDUMMY_WOUT_R::new(((self.bits >> 23) & 1) != 0)
164 }
165 #[doc = "Bit 24 - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller."]
166 #[inline(always)]
167 pub fn spi_smem_wdummy_dqs_always_out(&self) -> SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_R {
168 SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_R::new(((self.bits >> 24) & 1) != 0)
169 }
170 #[doc = "Bit 25 - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO\\[7:0\\] is output by the MSPI controller."]
171 #[inline(always)]
172 pub fn spi_smem_wdummy_always_out(&self) -> SPI_SMEM_WDUMMY_ALWAYS_OUT_R {
173 SPI_SMEM_WDUMMY_ALWAYS_OUT_R::new(((self.bits >> 25) & 1) != 0)
174 }
175 #[doc = "Bit 26 - For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable."]
176 #[inline(always)]
177 pub fn sdin_hex(&self) -> SDIN_HEX_R {
178 SDIN_HEX_R::new(((self.bits >> 26) & 1) != 0)
179 }
180 #[doc = "Bit 27 - For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable."]
181 #[inline(always)]
182 pub fn sdout_hex(&self) -> SDOUT_HEX_R {
183 SDOUT_HEX_R::new(((self.bits >> 27) & 1) != 0)
184 }
185 #[doc = "Bit 30 - When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others."]
186 #[inline(always)]
187 pub fn spi_smem_dqs_ie_always_on(&self) -> SPI_SMEM_DQS_IE_ALWAYS_ON_R {
188 SPI_SMEM_DQS_IE_ALWAYS_ON_R::new(((self.bits >> 30) & 1) != 0)
189 }
190 #[doc = "Bit 31 - When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO\\[7:0\\] are always 1. 0: Others."]
191 #[inline(always)]
192 pub fn spi_smem_data_ie_always_on(&self) -> SPI_SMEM_DATA_IE_ALWAYS_ON_R {
193 SPI_SMEM_DATA_IE_ALWAYS_ON_R::new(((self.bits >> 31) & 1) != 0)
194 }
195}
196#[cfg(feature = "impl-register-debug")]
197impl core::fmt::Debug for R {
198 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
199 f.debug_struct("SRAM_CMD")
200 .field("sclk_mode", &format_args!("{}", self.sclk_mode().bits()))
201 .field("swb_mode", &format_args!("{}", self.swb_mode().bits()))
202 .field("sdin_dual", &format_args!("{}", self.sdin_dual().bit()))
203 .field("sdout_dual", &format_args!("{}", self.sdout_dual().bit()))
204 .field("saddr_dual", &format_args!("{}", self.saddr_dual().bit()))
205 .field("sdin_quad", &format_args!("{}", self.sdin_quad().bit()))
206 .field("sdout_quad", &format_args!("{}", self.sdout_quad().bit()))
207 .field("saddr_quad", &format_args!("{}", self.saddr_quad().bit()))
208 .field("scmd_quad", &format_args!("{}", self.scmd_quad().bit()))
209 .field("sdin_oct", &format_args!("{}", self.sdin_oct().bit()))
210 .field("sdout_oct", &format_args!("{}", self.sdout_oct().bit()))
211 .field("saddr_oct", &format_args!("{}", self.saddr_oct().bit()))
212 .field("scmd_oct", &format_args!("{}", self.scmd_oct().bit()))
213 .field("sdummy_rin", &format_args!("{}", self.sdummy_rin().bit()))
214 .field("sdummy_wout", &format_args!("{}", self.sdummy_wout().bit()))
215 .field(
216 "spi_smem_wdummy_dqs_always_out",
217 &format_args!("{}", self.spi_smem_wdummy_dqs_always_out().bit()),
218 )
219 .field(
220 "spi_smem_wdummy_always_out",
221 &format_args!("{}", self.spi_smem_wdummy_always_out().bit()),
222 )
223 .field("sdin_hex", &format_args!("{}", self.sdin_hex().bit()))
224 .field("sdout_hex", &format_args!("{}", self.sdout_hex().bit()))
225 .field(
226 "spi_smem_dqs_ie_always_on",
227 &format_args!("{}", self.spi_smem_dqs_ie_always_on().bit()),
228 )
229 .field(
230 "spi_smem_data_ie_always_on",
231 &format_args!("{}", self.spi_smem_data_ie_always_on().bit()),
232 )
233 .finish()
234 }
235}
236#[cfg(feature = "impl-register-debug")]
237impl core::fmt::Debug for crate::generic::Reg<SRAM_CMD_SPEC> {
238 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
239 core::fmt::Debug::fmt(&self.read(), f)
240 }
241}
242impl W {
243 #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on."]
244 #[inline(always)]
245 #[must_use]
246 pub fn sclk_mode(&mut self) -> SCLK_MODE_W<SRAM_CMD_SPEC> {
247 SCLK_MODE_W::new(self, 0)
248 }
249 #[doc = "Bits 2:9 - Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit."]
250 #[inline(always)]
251 #[must_use]
252 pub fn swb_mode(&mut self) -> SWB_MODE_W<SRAM_CMD_SPEC> {
253 SWB_MODE_W::new(self, 2)
254 }
255 #[doc = "Bit 10 - For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."]
256 #[inline(always)]
257 #[must_use]
258 pub fn sdin_dual(&mut self) -> SDIN_DUAL_W<SRAM_CMD_SPEC> {
259 SDIN_DUAL_W::new(self, 10)
260 }
261 #[doc = "Bit 11 - For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."]
262 #[inline(always)]
263 #[must_use]
264 pub fn sdout_dual(&mut self) -> SDOUT_DUAL_W<SRAM_CMD_SPEC> {
265 SDOUT_DUAL_W::new(self, 11)
266 }
267 #[doc = "Bit 12 - For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."]
268 #[inline(always)]
269 #[must_use]
270 pub fn saddr_dual(&mut self) -> SADDR_DUAL_W<SRAM_CMD_SPEC> {
271 SADDR_DUAL_W::new(self, 12)
272 }
273 #[doc = "Bit 14 - For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
274 #[inline(always)]
275 #[must_use]
276 pub fn sdin_quad(&mut self) -> SDIN_QUAD_W<SRAM_CMD_SPEC> {
277 SDIN_QUAD_W::new(self, 14)
278 }
279 #[doc = "Bit 15 - For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
280 #[inline(always)]
281 #[must_use]
282 pub fn sdout_quad(&mut self) -> SDOUT_QUAD_W<SRAM_CMD_SPEC> {
283 SDOUT_QUAD_W::new(self, 15)
284 }
285 #[doc = "Bit 16 - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
286 #[inline(always)]
287 #[must_use]
288 pub fn saddr_quad(&mut self) -> SADDR_QUAD_W<SRAM_CMD_SPEC> {
289 SADDR_QUAD_W::new(self, 16)
290 }
291 #[doc = "Bit 17 - For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
292 #[inline(always)]
293 #[must_use]
294 pub fn scmd_quad(&mut self) -> SCMD_QUAD_W<SRAM_CMD_SPEC> {
295 SCMD_QUAD_W::new(self, 17)
296 }
297 #[doc = "Bit 18 - For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable."]
298 #[inline(always)]
299 #[must_use]
300 pub fn sdin_oct(&mut self) -> SDIN_OCT_W<SRAM_CMD_SPEC> {
301 SDIN_OCT_W::new(self, 18)
302 }
303 #[doc = "Bit 19 - For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable."]
304 #[inline(always)]
305 #[must_use]
306 pub fn sdout_oct(&mut self) -> SDOUT_OCT_W<SRAM_CMD_SPEC> {
307 SDOUT_OCT_W::new(self, 19)
308 }
309 #[doc = "Bit 20 - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable."]
310 #[inline(always)]
311 #[must_use]
312 pub fn saddr_oct(&mut self) -> SADDR_OCT_W<SRAM_CMD_SPEC> {
313 SADDR_OCT_W::new(self, 20)
314 }
315 #[doc = "Bit 21 - For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable."]
316 #[inline(always)]
317 #[must_use]
318 pub fn scmd_oct(&mut self) -> SCMD_OCT_W<SRAM_CMD_SPEC> {
319 SCMD_OCT_W::new(self, 21)
320 }
321 #[doc = "Bit 22 - In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."]
322 #[inline(always)]
323 #[must_use]
324 pub fn sdummy_rin(&mut self) -> SDUMMY_RIN_W<SRAM_CMD_SPEC> {
325 SDUMMY_RIN_W::new(self, 22)
326 }
327 #[doc = "Bit 23 - In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."]
328 #[inline(always)]
329 #[must_use]
330 pub fn sdummy_wout(&mut self) -> SDUMMY_WOUT_W<SRAM_CMD_SPEC> {
331 SDUMMY_WOUT_W::new(self, 23)
332 }
333 #[doc = "Bit 24 - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller."]
334 #[inline(always)]
335 #[must_use]
336 pub fn spi_smem_wdummy_dqs_always_out(
337 &mut self,
338 ) -> SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_W<SRAM_CMD_SPEC> {
339 SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_W::new(self, 24)
340 }
341 #[doc = "Bit 25 - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO\\[7:0\\] is output by the MSPI controller."]
342 #[inline(always)]
343 #[must_use]
344 pub fn spi_smem_wdummy_always_out(&mut self) -> SPI_SMEM_WDUMMY_ALWAYS_OUT_W<SRAM_CMD_SPEC> {
345 SPI_SMEM_WDUMMY_ALWAYS_OUT_W::new(self, 25)
346 }
347 #[doc = "Bit 26 - For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable."]
348 #[inline(always)]
349 #[must_use]
350 pub fn sdin_hex(&mut self) -> SDIN_HEX_W<SRAM_CMD_SPEC> {
351 SDIN_HEX_W::new(self, 26)
352 }
353 #[doc = "Bit 27 - For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable."]
354 #[inline(always)]
355 #[must_use]
356 pub fn sdout_hex(&mut self) -> SDOUT_HEX_W<SRAM_CMD_SPEC> {
357 SDOUT_HEX_W::new(self, 27)
358 }
359 #[doc = "Bit 30 - When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others."]
360 #[inline(always)]
361 #[must_use]
362 pub fn spi_smem_dqs_ie_always_on(&mut self) -> SPI_SMEM_DQS_IE_ALWAYS_ON_W<SRAM_CMD_SPEC> {
363 SPI_SMEM_DQS_IE_ALWAYS_ON_W::new(self, 30)
364 }
365 #[doc = "Bit 31 - When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO\\[7:0\\] are always 1. 0: Others."]
366 #[inline(always)]
367 #[must_use]
368 pub fn spi_smem_data_ie_always_on(&mut self) -> SPI_SMEM_DATA_IE_ALWAYS_ON_W<SRAM_CMD_SPEC> {
369 SPI_SMEM_DATA_IE_ALWAYS_ON_W::new(self, 31)
370 }
371}
372#[doc = "SPI0 external RAM mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sram_cmd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sram_cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
373pub struct SRAM_CMD_SPEC;
374impl crate::RegisterSpec for SRAM_CMD_SPEC {
375 type Ux = u32;
376}
377#[doc = "`read()` method returns [`sram_cmd::R`](R) reader structure"]
378impl crate::Readable for SRAM_CMD_SPEC {}
379#[doc = "`write(|w| ..)` method takes [`sram_cmd::W`](W) writer structure"]
380impl crate::Writable for SRAM_CMD_SPEC {
381 type Safety = crate::Unsafe;
382 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
383 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
384}
385#[doc = "`reset()` method sets SRAM_CMD to value 0x80c0_0000"]
386impl crate::Resettable for SRAM_CMD_SPEC {
387 const RESET_VALUE: u32 = 0x80c0_0000;
388}