esp32p4/spi0/
spi_smem_pms_attr.rs

1#[doc = "Register `SPI_SMEM_PMS%s_ATTR` reader"]
2pub type R = crate::R<SPI_SMEM_PMS_ATTR_SPEC>;
3#[doc = "Register `SPI_SMEM_PMS%s_ATTR` writer"]
4pub type W = crate::W<SPI_SMEM_PMS_ATTR_SPEC>;
5#[doc = "Field `SPI_SMEM_PMS_RD_ATTR` reader - 1: SPI1 external RAM PMS section %s read accessible. 0: Not allowed."]
6pub type SPI_SMEM_PMS_RD_ATTR_R = crate::BitReader;
7#[doc = "Field `SPI_SMEM_PMS_RD_ATTR` writer - 1: SPI1 external RAM PMS section %s read accessible. 0: Not allowed."]
8pub type SPI_SMEM_PMS_RD_ATTR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SPI_SMEM_PMS_WR_ATTR` reader - 1: SPI1 external RAM PMS section %s write accessible. 0: Not allowed."]
10pub type SPI_SMEM_PMS_WR_ATTR_R = crate::BitReader;
11#[doc = "Field `SPI_SMEM_PMS_WR_ATTR` writer - 1: SPI1 external RAM PMS section %s write accessible. 0: Not allowed."]
12pub type SPI_SMEM_PMS_WR_ATTR_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SPI_SMEM_PMS_ECC` reader - SPI1 external RAM PMS section %s ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section %s is configured by registers SPI_SMEM_PMS%s_ADDR_REG and SPI_SMEM_PMS%s_SIZE_REG."]
14pub type SPI_SMEM_PMS_ECC_R = crate::BitReader;
15#[doc = "Field `SPI_SMEM_PMS_ECC` writer - SPI1 external RAM PMS section %s ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section %s is configured by registers SPI_SMEM_PMS%s_ADDR_REG and SPI_SMEM_PMS%s_SIZE_REG."]
16pub type SPI_SMEM_PMS_ECC_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bit 0 - 1: SPI1 external RAM PMS section %s read accessible. 0: Not allowed."]
19    #[inline(always)]
20    pub fn spi_smem_pms_rd_attr(&self) -> SPI_SMEM_PMS_RD_ATTR_R {
21        SPI_SMEM_PMS_RD_ATTR_R::new((self.bits & 1) != 0)
22    }
23    #[doc = "Bit 1 - 1: SPI1 external RAM PMS section %s write accessible. 0: Not allowed."]
24    #[inline(always)]
25    pub fn spi_smem_pms_wr_attr(&self) -> SPI_SMEM_PMS_WR_ATTR_R {
26        SPI_SMEM_PMS_WR_ATTR_R::new(((self.bits >> 1) & 1) != 0)
27    }
28    #[doc = "Bit 2 - SPI1 external RAM PMS section %s ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section %s is configured by registers SPI_SMEM_PMS%s_ADDR_REG and SPI_SMEM_PMS%s_SIZE_REG."]
29    #[inline(always)]
30    pub fn spi_smem_pms_ecc(&self) -> SPI_SMEM_PMS_ECC_R {
31        SPI_SMEM_PMS_ECC_R::new(((self.bits >> 2) & 1) != 0)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("SPI_SMEM_PMS_ATTR")
38            .field(
39                "spi_smem_pms_rd_attr",
40                &format_args!("{}", self.spi_smem_pms_rd_attr().bit()),
41            )
42            .field(
43                "spi_smem_pms_wr_attr",
44                &format_args!("{}", self.spi_smem_pms_wr_attr().bit()),
45            )
46            .field(
47                "spi_smem_pms_ecc",
48                &format_args!("{}", self.spi_smem_pms_ecc().bit()),
49            )
50            .finish()
51    }
52}
53#[cfg(feature = "impl-register-debug")]
54impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_PMS_ATTR_SPEC> {
55    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
56        core::fmt::Debug::fmt(&self.read(), f)
57    }
58}
59impl W {
60    #[doc = "Bit 0 - 1: SPI1 external RAM PMS section %s read accessible. 0: Not allowed."]
61    #[inline(always)]
62    #[must_use]
63    pub fn spi_smem_pms_rd_attr(&mut self) -> SPI_SMEM_PMS_RD_ATTR_W<SPI_SMEM_PMS_ATTR_SPEC> {
64        SPI_SMEM_PMS_RD_ATTR_W::new(self, 0)
65    }
66    #[doc = "Bit 1 - 1: SPI1 external RAM PMS section %s write accessible. 0: Not allowed."]
67    #[inline(always)]
68    #[must_use]
69    pub fn spi_smem_pms_wr_attr(&mut self) -> SPI_SMEM_PMS_WR_ATTR_W<SPI_SMEM_PMS_ATTR_SPEC> {
70        SPI_SMEM_PMS_WR_ATTR_W::new(self, 1)
71    }
72    #[doc = "Bit 2 - SPI1 external RAM PMS section %s ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section %s is configured by registers SPI_SMEM_PMS%s_ADDR_REG and SPI_SMEM_PMS%s_SIZE_REG."]
73    #[inline(always)]
74    #[must_use]
75    pub fn spi_smem_pms_ecc(&mut self) -> SPI_SMEM_PMS_ECC_W<SPI_SMEM_PMS_ATTR_SPEC> {
76        SPI_SMEM_PMS_ECC_W::new(self, 2)
77    }
78}
79#[doc = "SPI1 flash PMS section %s start address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_pms_attr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_pms_attr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
80pub struct SPI_SMEM_PMS_ATTR_SPEC;
81impl crate::RegisterSpec for SPI_SMEM_PMS_ATTR_SPEC {
82    type Ux = u32;
83}
84#[doc = "`read()` method returns [`spi_smem_pms_attr::R`](R) reader structure"]
85impl crate::Readable for SPI_SMEM_PMS_ATTR_SPEC {}
86#[doc = "`write(|w| ..)` method takes [`spi_smem_pms_attr::W`](W) writer structure"]
87impl crate::Writable for SPI_SMEM_PMS_ATTR_SPEC {
88    type Safety = crate::Unsafe;
89    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
90    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
91}
92#[doc = "`reset()` method sets SPI_SMEM_PMS%s_ATTR to value 0x03"]
93impl crate::Resettable for SPI_SMEM_PMS_ATTR_SPEC {
94    const RESET_VALUE: u32 = 0x03;
95}
esp32p4/spi0/spi_smem_pms_attr.rs

esp32p4/spi0/
spi_smem_pms_attr.rs
