esp32p4/sdhost/
mintsts.rs

1#[doc = "Register `MINTSTS` reader"]
2pub type R = crate::R<MINTSTS_SPEC>;
3#[doc = "Field `INT_STATUS_MSK` reader - Interrupt enabled only if corresponding bit in interrupt mask register is set. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): RX Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation by host timeout (HTO); Bit 9 (DTRO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."]
4pub type INT_STATUS_MSK_R = crate::FieldReader<u16>;
5#[doc = "Field `SDIO_INTERRUPT_MSK` reader - Interrupt from SDIO card, one bit for each card. Bit\\[17:16\\] correspond to card1 and card0, respectively. SDIO interrupt for card is enabled only if corresponding sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit enables interrupt)."]
6pub type SDIO_INTERRUPT_MSK_R = crate::FieldReader;
7impl R {
8    #[doc = "Bits 0:15 - Interrupt enabled only if corresponding bit in interrupt mask register is set. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): RX Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation by host timeout (HTO); Bit 9 (DTRO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."]
9    #[inline(always)]
10    pub fn int_status_msk(&self) -> INT_STATUS_MSK_R {
11        INT_STATUS_MSK_R::new((self.bits & 0xffff) as u16)
12    }
13    #[doc = "Bits 16:17 - Interrupt from SDIO card, one bit for each card. Bit\\[17:16\\] correspond to card1 and card0, respectively. SDIO interrupt for card is enabled only if corresponding sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit enables interrupt)."]
14    #[inline(always)]
15    pub fn sdio_interrupt_msk(&self) -> SDIO_INTERRUPT_MSK_R {
16        SDIO_INTERRUPT_MSK_R::new(((self.bits >> 16) & 3) as u8)
17    }
18}
19#[cfg(feature = "impl-register-debug")]
20impl core::fmt::Debug for R {
21    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22        f.debug_struct("MINTSTS")
23            .field(
24                "int_status_msk",
25                &format_args!("{}", self.int_status_msk().bits()),
26            )
27            .field(
28                "sdio_interrupt_msk",
29                &format_args!("{}", self.sdio_interrupt_msk().bits()),
30            )
31            .finish()
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for crate::generic::Reg<MINTSTS_SPEC> {
36    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
37        core::fmt::Debug::fmt(&self.read(), f)
38    }
39}
40#[doc = "Masked interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mintsts::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
41pub struct MINTSTS_SPEC;
42impl crate::RegisterSpec for MINTSTS_SPEC {
43    type Ux = u32;
44}
45#[doc = "`read()` method returns [`mintsts::R`](R) reader structure"]
46impl crate::Readable for MINTSTS_SPEC {}
47#[doc = "`reset()` method sets MINTSTS to value 0"]
48impl crate::Resettable for MINTSTS_SPEC {
49    const RESET_VALUE: u32 = 0;
50}
esp32p4/sdhost/mintsts.rs

esp32p4/sdhost/
mintsts.rs
