esp32p4/pmu/
power_ck_wait_cntl.rs

1#[doc = "Register `POWER_CK_WAIT_CNTL` reader"]
2pub type R = crate::R<POWER_CK_WAIT_CNTL_SPEC>;
3#[doc = "Register `POWER_CK_WAIT_CNTL` writer"]
4pub type W = crate::W<POWER_CK_WAIT_CNTL_SPEC>;
5#[doc = "Field `PMU_WAIT_XTL_STABLE` reader - need_des"]
6pub type PMU_WAIT_XTL_STABLE_R = crate::FieldReader<u16>;
7#[doc = "Field `PMU_WAIT_XTL_STABLE` writer - need_des"]
8pub type PMU_WAIT_XTL_STABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9#[doc = "Field `PMU_WAIT_PLL_STABLE` reader - need_des"]
10pub type PMU_WAIT_PLL_STABLE_R = crate::FieldReader<u16>;
11#[doc = "Field `PMU_WAIT_PLL_STABLE` writer - need_des"]
12pub type PMU_WAIT_PLL_STABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13impl R {
14    #[doc = "Bits 0:15 - need_des"]
15    #[inline(always)]
16    pub fn pmu_wait_xtl_stable(&self) -> PMU_WAIT_XTL_STABLE_R {
17        PMU_WAIT_XTL_STABLE_R::new((self.bits & 0xffff) as u16)
18    }
19    #[doc = "Bits 16:31 - need_des"]
20    #[inline(always)]
21    pub fn pmu_wait_pll_stable(&self) -> PMU_WAIT_PLL_STABLE_R {
22        PMU_WAIT_PLL_STABLE_R::new(((self.bits >> 16) & 0xffff) as u16)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("POWER_CK_WAIT_CNTL")
29            .field(
30                "pmu_wait_xtl_stable",
31                &format_args!("{}", self.pmu_wait_xtl_stable().bits()),
32            )
33            .field(
34                "pmu_wait_pll_stable",
35                &format_args!("{}", self.pmu_wait_pll_stable().bits()),
36            )
37            .finish()
38    }
39}
40#[cfg(feature = "impl-register-debug")]
41impl core::fmt::Debug for crate::generic::Reg<POWER_CK_WAIT_CNTL_SPEC> {
42    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
43        core::fmt::Debug::fmt(&self.read(), f)
44    }
45}
46impl W {
47    #[doc = "Bits 0:15 - need_des"]
48    #[inline(always)]
49    #[must_use]
50    pub fn pmu_wait_xtl_stable(&mut self) -> PMU_WAIT_XTL_STABLE_W<POWER_CK_WAIT_CNTL_SPEC> {
51        PMU_WAIT_XTL_STABLE_W::new(self, 0)
52    }
53    #[doc = "Bits 16:31 - need_des"]
54    #[inline(always)]
55    #[must_use]
56    pub fn pmu_wait_pll_stable(&mut self) -> PMU_WAIT_PLL_STABLE_W<POWER_CK_WAIT_CNTL_SPEC> {
57        PMU_WAIT_PLL_STABLE_W::new(self, 16)
58    }
59}
60#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_ck_wait_cntl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_ck_wait_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
61pub struct POWER_CK_WAIT_CNTL_SPEC;
62impl crate::RegisterSpec for POWER_CK_WAIT_CNTL_SPEC {
63    type Ux = u32;
64}
65#[doc = "`read()` method returns [`power_ck_wait_cntl::R`](R) reader structure"]
66impl crate::Readable for POWER_CK_WAIT_CNTL_SPEC {}
67#[doc = "`write(|w| ..)` method takes [`power_ck_wait_cntl::W`](W) writer structure"]
68impl crate::Writable for POWER_CK_WAIT_CNTL_SPEC {
69    type Safety = crate::Unsafe;
70    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
71    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
72}
73#[doc = "`reset()` method sets POWER_CK_WAIT_CNTL to value 0x0100_0100"]
74impl crate::Resettable for POWER_CK_WAIT_CNTL_SPEC {
75    const RESET_VALUE: u32 = 0x0100_0100;
76}
esp32p4/pmu/power_ck_wait_cntl.rs

esp32p4/pmu/
power_ck_wait_cntl.rs
