esp32p4/pmu/
hp_ck_cntl.rs

1#[doc = "Register `HP_CK_CNTL` reader"]
2pub type R = crate::R<HP_CK_CNTL_SPEC>;
3#[doc = "Register `HP_CK_CNTL` writer"]
4pub type W = crate::W<HP_CK_CNTL_SPEC>;
5#[doc = "Field `MODIFY_ICG_CNTL_WAIT` reader - need_des"]
6pub type MODIFY_ICG_CNTL_WAIT_R = crate::FieldReader;
7#[doc = "Field `MODIFY_ICG_CNTL_WAIT` writer - need_des"]
8pub type MODIFY_ICG_CNTL_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `SWITCH_ICG_CNTL_WAIT` reader - need_des"]
10pub type SWITCH_ICG_CNTL_WAIT_R = crate::FieldReader;
11#[doc = "Field `SWITCH_ICG_CNTL_WAIT` writer - need_des"]
12pub type SWITCH_ICG_CNTL_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13impl R {
14    #[doc = "Bits 0:7 - need_des"]
15    #[inline(always)]
16    pub fn modify_icg_cntl_wait(&self) -> MODIFY_ICG_CNTL_WAIT_R {
17        MODIFY_ICG_CNTL_WAIT_R::new((self.bits & 0xff) as u8)
18    }
19    #[doc = "Bits 8:15 - need_des"]
20    #[inline(always)]
21    pub fn switch_icg_cntl_wait(&self) -> SWITCH_ICG_CNTL_WAIT_R {
22        SWITCH_ICG_CNTL_WAIT_R::new(((self.bits >> 8) & 0xff) as u8)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("HP_CK_CNTL")
29            .field(
30                "modify_icg_cntl_wait",
31                &format_args!("{}", self.modify_icg_cntl_wait().bits()),
32            )
33            .field(
34                "switch_icg_cntl_wait",
35                &format_args!("{}", self.switch_icg_cntl_wait().bits()),
36            )
37            .finish()
38    }
39}
40#[cfg(feature = "impl-register-debug")]
41impl core::fmt::Debug for crate::generic::Reg<HP_CK_CNTL_SPEC> {
42    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
43        core::fmt::Debug::fmt(&self.read(), f)
44    }
45}
46impl W {
47    #[doc = "Bits 0:7 - need_des"]
48    #[inline(always)]
49    #[must_use]
50    pub fn modify_icg_cntl_wait(&mut self) -> MODIFY_ICG_CNTL_WAIT_W<HP_CK_CNTL_SPEC> {
51        MODIFY_ICG_CNTL_WAIT_W::new(self, 0)
52    }
53    #[doc = "Bits 8:15 - need_des"]
54    #[inline(always)]
55    #[must_use]
56    pub fn switch_icg_cntl_wait(&mut self) -> SWITCH_ICG_CNTL_WAIT_W<HP_CK_CNTL_SPEC> {
57        SWITCH_ICG_CNTL_WAIT_W::new(self, 8)
58    }
59}
60#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_ck_cntl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_ck_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
61pub struct HP_CK_CNTL_SPEC;
62impl crate::RegisterSpec for HP_CK_CNTL_SPEC {
63    type Ux = u32;
64}
65#[doc = "`read()` method returns [`hp_ck_cntl::R`](R) reader structure"]
66impl crate::Readable for HP_CK_CNTL_SPEC {}
67#[doc = "`write(|w| ..)` method takes [`hp_ck_cntl::W`](W) writer structure"]
68impl crate::Writable for HP_CK_CNTL_SPEC {
69    type Safety = crate::Unsafe;
70    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
71    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
72}
73#[doc = "`reset()` method sets HP_CK_CNTL to value 0x0a0a"]
74impl crate::Resettable for HP_CK_CNTL_SPEC {
75    const RESET_VALUE: u32 = 0x0a0a;
76}
esp32p4/pmu/hp_ck_cntl.rs

esp32p4/pmu/
hp_ck_cntl.rs
