esp32p4/mipi_dsi_host/
phy_ulps_ctrl.rs

1#[doc = "Register `PHY_ULPS_CTRL` reader"]
2pub type R = crate::R<PHY_ULPS_CTRL_SPEC>;
3#[doc = "Register `PHY_ULPS_CTRL` writer"]
4pub type W = crate::W<PHY_ULPS_CTRL_SPEC>;
5#[doc = "Field `PHY_TXREQULPSCLK` reader - NA"]
6pub type PHY_TXREQULPSCLK_R = crate::BitReader;
7#[doc = "Field `PHY_TXREQULPSCLK` writer - NA"]
8pub type PHY_TXREQULPSCLK_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PHY_TXEXITULPSCLK` reader - NA"]
10pub type PHY_TXEXITULPSCLK_R = crate::BitReader;
11#[doc = "Field `PHY_TXEXITULPSCLK` writer - NA"]
12pub type PHY_TXEXITULPSCLK_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PHY_TXREQULPSLAN` reader - NA"]
14pub type PHY_TXREQULPSLAN_R = crate::BitReader;
15#[doc = "Field `PHY_TXREQULPSLAN` writer - NA"]
16pub type PHY_TXREQULPSLAN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `PHY_TXEXITULPSLAN` reader - NA"]
18pub type PHY_TXEXITULPSLAN_R = crate::BitReader;
19#[doc = "Field `PHY_TXEXITULPSLAN` writer - NA"]
20pub type PHY_TXEXITULPSLAN_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 0 - NA"]
23    #[inline(always)]
24    pub fn phy_txrequlpsclk(&self) -> PHY_TXREQULPSCLK_R {
25        PHY_TXREQULPSCLK_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - NA"]
28    #[inline(always)]
29    pub fn phy_txexitulpsclk(&self) -> PHY_TXEXITULPSCLK_R {
30        PHY_TXEXITULPSCLK_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 2 - NA"]
33    #[inline(always)]
34    pub fn phy_txrequlpslan(&self) -> PHY_TXREQULPSLAN_R {
35        PHY_TXREQULPSLAN_R::new(((self.bits >> 2) & 1) != 0)
36    }
37    #[doc = "Bit 3 - NA"]
38    #[inline(always)]
39    pub fn phy_txexitulpslan(&self) -> PHY_TXEXITULPSLAN_R {
40        PHY_TXEXITULPSLAN_R::new(((self.bits >> 3) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("PHY_ULPS_CTRL")
47            .field(
48                "phy_txrequlpsclk",
49                &format_args!("{}", self.phy_txrequlpsclk().bit()),
50            )
51            .field(
52                "phy_txexitulpsclk",
53                &format_args!("{}", self.phy_txexitulpsclk().bit()),
54            )
55            .field(
56                "phy_txrequlpslan",
57                &format_args!("{}", self.phy_txrequlpslan().bit()),
58            )
59            .field(
60                "phy_txexitulpslan",
61                &format_args!("{}", self.phy_txexitulpslan().bit()),
62            )
63            .finish()
64    }
65}
66#[cfg(feature = "impl-register-debug")]
67impl core::fmt::Debug for crate::generic::Reg<PHY_ULPS_CTRL_SPEC> {
68    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
69        core::fmt::Debug::fmt(&self.read(), f)
70    }
71}
72impl W {
73    #[doc = "Bit 0 - NA"]
74    #[inline(always)]
75    #[must_use]
76    pub fn phy_txrequlpsclk(&mut self) -> PHY_TXREQULPSCLK_W<PHY_ULPS_CTRL_SPEC> {
77        PHY_TXREQULPSCLK_W::new(self, 0)
78    }
79    #[doc = "Bit 1 - NA"]
80    #[inline(always)]
81    #[must_use]
82    pub fn phy_txexitulpsclk(&mut self) -> PHY_TXEXITULPSCLK_W<PHY_ULPS_CTRL_SPEC> {
83        PHY_TXEXITULPSCLK_W::new(self, 1)
84    }
85    #[doc = "Bit 2 - NA"]
86    #[inline(always)]
87    #[must_use]
88    pub fn phy_txrequlpslan(&mut self) -> PHY_TXREQULPSLAN_W<PHY_ULPS_CTRL_SPEC> {
89        PHY_TXREQULPSLAN_W::new(self, 2)
90    }
91    #[doc = "Bit 3 - NA"]
92    #[inline(always)]
93    #[must_use]
94    pub fn phy_txexitulpslan(&mut self) -> PHY_TXEXITULPSLAN_W<PHY_ULPS_CTRL_SPEC> {
95        PHY_TXEXITULPSLAN_W::new(self, 3)
96    }
97}
98#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_ulps_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_ulps_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
99pub struct PHY_ULPS_CTRL_SPEC;
100impl crate::RegisterSpec for PHY_ULPS_CTRL_SPEC {
101    type Ux = u32;
102}
103#[doc = "`read()` method returns [`phy_ulps_ctrl::R`](R) reader structure"]
104impl crate::Readable for PHY_ULPS_CTRL_SPEC {}
105#[doc = "`write(|w| ..)` method takes [`phy_ulps_ctrl::W`](W) writer structure"]
106impl crate::Writable for PHY_ULPS_CTRL_SPEC {
107    type Safety = crate::Unsafe;
108    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
109    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
110}
111#[doc = "`reset()` method sets PHY_ULPS_CTRL to value 0"]
112impl crate::Resettable for PHY_ULPS_CTRL_SPEC {
113    const RESET_VALUE: u32 = 0;
114}
esp32p4/mipi_dsi_host/phy_ulps_ctrl.rs

esp32p4/mipi_dsi_host/
phy_ulps_ctrl.rs
