esp32p4/mipi_dsi_host/
phy_rstz.rs

1#[doc = "Register `PHY_RSTZ` reader"]
2pub type R = crate::R<PHY_RSTZ_SPEC>;
3#[doc = "Register `PHY_RSTZ` writer"]
4pub type W = crate::W<PHY_RSTZ_SPEC>;
5#[doc = "Field `PHY_SHUTDOWNZ` reader - NA"]
6pub type PHY_SHUTDOWNZ_R = crate::BitReader;
7#[doc = "Field `PHY_SHUTDOWNZ` writer - NA"]
8pub type PHY_SHUTDOWNZ_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PHY_RSTZ` reader - NA"]
10pub type PHY_RSTZ_R = crate::BitReader;
11#[doc = "Field `PHY_RSTZ` writer - NA"]
12pub type PHY_RSTZ_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PHY_ENABLECLK` reader - NA"]
14pub type PHY_ENABLECLK_R = crate::BitReader;
15#[doc = "Field `PHY_ENABLECLK` writer - NA"]
16pub type PHY_ENABLECLK_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `PHY_FORCEPLL` reader - NA"]
18pub type PHY_FORCEPLL_R = crate::BitReader;
19#[doc = "Field `PHY_FORCEPLL` writer - NA"]
20pub type PHY_FORCEPLL_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 0 - NA"]
23    #[inline(always)]
24    pub fn phy_shutdownz(&self) -> PHY_SHUTDOWNZ_R {
25        PHY_SHUTDOWNZ_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - NA"]
28    #[inline(always)]
29    pub fn phy_rstz(&self) -> PHY_RSTZ_R {
30        PHY_RSTZ_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 2 - NA"]
33    #[inline(always)]
34    pub fn phy_enableclk(&self) -> PHY_ENABLECLK_R {
35        PHY_ENABLECLK_R::new(((self.bits >> 2) & 1) != 0)
36    }
37    #[doc = "Bit 3 - NA"]
38    #[inline(always)]
39    pub fn phy_forcepll(&self) -> PHY_FORCEPLL_R {
40        PHY_FORCEPLL_R::new(((self.bits >> 3) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("PHY_RSTZ")
47            .field(
48                "phy_shutdownz",
49                &format_args!("{}", self.phy_shutdownz().bit()),
50            )
51            .field("phy_rstz", &format_args!("{}", self.phy_rstz().bit()))
52            .field(
53                "phy_enableclk",
54                &format_args!("{}", self.phy_enableclk().bit()),
55            )
56            .field(
57                "phy_forcepll",
58                &format_args!("{}", self.phy_forcepll().bit()),
59            )
60            .finish()
61    }
62}
63#[cfg(feature = "impl-register-debug")]
64impl core::fmt::Debug for crate::generic::Reg<PHY_RSTZ_SPEC> {
65    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
66        core::fmt::Debug::fmt(&self.read(), f)
67    }
68}
69impl W {
70    #[doc = "Bit 0 - NA"]
71    #[inline(always)]
72    #[must_use]
73    pub fn phy_shutdownz(&mut self) -> PHY_SHUTDOWNZ_W<PHY_RSTZ_SPEC> {
74        PHY_SHUTDOWNZ_W::new(self, 0)
75    }
76    #[doc = "Bit 1 - NA"]
77    #[inline(always)]
78    #[must_use]
79    pub fn phy_rstz(&mut self) -> PHY_RSTZ_W<PHY_RSTZ_SPEC> {
80        PHY_RSTZ_W::new(self, 1)
81    }
82    #[doc = "Bit 2 - NA"]
83    #[inline(always)]
84    #[must_use]
85    pub fn phy_enableclk(&mut self) -> PHY_ENABLECLK_W<PHY_RSTZ_SPEC> {
86        PHY_ENABLECLK_W::new(self, 2)
87    }
88    #[doc = "Bit 3 - NA"]
89    #[inline(always)]
90    #[must_use]
91    pub fn phy_forcepll(&mut self) -> PHY_FORCEPLL_W<PHY_RSTZ_SPEC> {
92        PHY_FORCEPLL_W::new(self, 3)
93    }
94}
95#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_rstz::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_rstz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
96pub struct PHY_RSTZ_SPEC;
97impl crate::RegisterSpec for PHY_RSTZ_SPEC {
98    type Ux = u32;
99}
100#[doc = "`read()` method returns [`phy_rstz::R`](R) reader structure"]
101impl crate::Readable for PHY_RSTZ_SPEC {}
102#[doc = "`write(|w| ..)` method takes [`phy_rstz::W`](W) writer structure"]
103impl crate::Writable for PHY_RSTZ_SPEC {
104    type Safety = crate::Unsafe;
105    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
106    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
107}
108#[doc = "`reset()` method sets PHY_RSTZ to value 0"]
109impl crate::Resettable for PHY_RSTZ_SPEC {
110    const RESET_VALUE: u32 = 0;
111}
esp32p4/mipi_dsi_host/phy_rstz.rs

esp32p4/mipi_dsi_host/
phy_rstz.rs
