esp32p4/mipi_dsi_bridge/
raw_buf_credit_ctl.rs

1#[doc = "Register `RAW_BUF_CREDIT_CTL` reader"]
2pub type R = crate::R<RAW_BUF_CREDIT_CTL_SPEC>;
3#[doc = "Register `RAW_BUF_CREDIT_CTL` writer"]
4pub type W = crate::W<RAW_BUF_CREDIT_CTL_SPEC>;
5#[doc = "Field `CREDIT_THRD` reader - this field configures the threshold whether dsi_bridge fifo can receive one more 64-bit, valid only when dsi_bridge as flow controller"]
6pub type CREDIT_THRD_R = crate::FieldReader<u16>;
7#[doc = "Field `CREDIT_THRD` writer - this field configures the threshold whether dsi_bridge fifo can receive one more 64-bit, valid only when dsi_bridge as flow controller"]
8pub type CREDIT_THRD_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
9#[doc = "Field `CREDIT_BURST_THRD` reader - this field configures the threshold whether dsi_bridge fifo can receive one more dma burst, valid only when dsi_bridge as flow controller"]
10pub type CREDIT_BURST_THRD_R = crate::FieldReader<u16>;
11#[doc = "Field `CREDIT_BURST_THRD` writer - this field configures the threshold whether dsi_bridge fifo can receive one more dma burst, valid only when dsi_bridge as flow controller"]
12pub type CREDIT_BURST_THRD_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
13#[doc = "Field `CREDIT_RESET` reader - this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when dsi_bridge as flow controller"]
14pub type CREDIT_RESET_R = crate::BitReader;
15#[doc = "Field `CREDIT_RESET` writer - this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when dsi_bridge as flow controller"]
16pub type CREDIT_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bits 0:14 - this field configures the threshold whether dsi_bridge fifo can receive one more 64-bit, valid only when dsi_bridge as flow controller"]
19    #[inline(always)]
20    pub fn credit_thrd(&self) -> CREDIT_THRD_R {
21        CREDIT_THRD_R::new((self.bits & 0x7fff) as u16)
22    }
23    #[doc = "Bits 16:30 - this field configures the threshold whether dsi_bridge fifo can receive one more dma burst, valid only when dsi_bridge as flow controller"]
24    #[inline(always)]
25    pub fn credit_burst_thrd(&self) -> CREDIT_BURST_THRD_R {
26        CREDIT_BURST_THRD_R::new(((self.bits >> 16) & 0x7fff) as u16)
27    }
28    #[doc = "Bit 31 - this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when dsi_bridge as flow controller"]
29    #[inline(always)]
30    pub fn credit_reset(&self) -> CREDIT_RESET_R {
31        CREDIT_RESET_R::new(((self.bits >> 31) & 1) != 0)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("RAW_BUF_CREDIT_CTL")
38            .field(
39                "credit_thrd",
40                &format_args!("{}", self.credit_thrd().bits()),
41            )
42            .field(
43                "credit_burst_thrd",
44                &format_args!("{}", self.credit_burst_thrd().bits()),
45            )
46            .field(
47                "credit_reset",
48                &format_args!("{}", self.credit_reset().bit()),
49            )
50            .finish()
51    }
52}
53#[cfg(feature = "impl-register-debug")]
54impl core::fmt::Debug for crate::generic::Reg<RAW_BUF_CREDIT_CTL_SPEC> {
55    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
56        core::fmt::Debug::fmt(&self.read(), f)
57    }
58}
59impl W {
60    #[doc = "Bits 0:14 - this field configures the threshold whether dsi_bridge fifo can receive one more 64-bit, valid only when dsi_bridge as flow controller"]
61    #[inline(always)]
62    #[must_use]
63    pub fn credit_thrd(&mut self) -> CREDIT_THRD_W<RAW_BUF_CREDIT_CTL_SPEC> {
64        CREDIT_THRD_W::new(self, 0)
65    }
66    #[doc = "Bits 16:30 - this field configures the threshold whether dsi_bridge fifo can receive one more dma burst, valid only when dsi_bridge as flow controller"]
67    #[inline(always)]
68    #[must_use]
69    pub fn credit_burst_thrd(&mut self) -> CREDIT_BURST_THRD_W<RAW_BUF_CREDIT_CTL_SPEC> {
70        CREDIT_BURST_THRD_W::new(self, 16)
71    }
72    #[doc = "Bit 31 - this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when dsi_bridge as flow controller"]
73    #[inline(always)]
74    #[must_use]
75    pub fn credit_reset(&mut self) -> CREDIT_RESET_W<RAW_BUF_CREDIT_CTL_SPEC> {
76        CREDIT_RESET_W::new(self, 31)
77    }
78}
79#[doc = "dsi bridge credit register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_buf_credit_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_buf_credit_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
80pub struct RAW_BUF_CREDIT_CTL_SPEC;
81impl crate::RegisterSpec for RAW_BUF_CREDIT_CTL_SPEC {
82    type Ux = u32;
83}
84#[doc = "`read()` method returns [`raw_buf_credit_ctl::R`](R) reader structure"]
85impl crate::Readable for RAW_BUF_CREDIT_CTL_SPEC {}
86#[doc = "`write(|w| ..)` method takes [`raw_buf_credit_ctl::W`](W) writer structure"]
87impl crate::Writable for RAW_BUF_CREDIT_CTL_SPEC {
88    type Safety = crate::Unsafe;
89    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
90    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
91}
92#[doc = "`reset()` method sets RAW_BUF_CREDIT_CTL to value 0x0320_0400"]
93impl crate::Resettable for RAW_BUF_CREDIT_CTL_SPEC {
94    const RESET_VALUE: u32 = 0x0320_0400;
95}
esp32p4/mipi_dsi_bridge/raw_buf_credit_ctl.rs

esp32p4/mipi_dsi_bridge/
raw_buf_credit_ctl.rs
