esp32p4/mipi_dsi_bridge/
int_st.rs

1#[doc = "Register `INT_ST` reader"]
2pub type R = crate::R<INT_ST_SPEC>;
3#[doc = "Field `UNDERRUN` reader - the masked interrupt status of dpi_underrun"]
4pub type UNDERRUN_R = crate::BitReader;
5impl R {
6    #[doc = "Bit 0 - the masked interrupt status of dpi_underrun"]
7    #[inline(always)]
8    pub fn underrun(&self) -> UNDERRUN_R {
9        UNDERRUN_R::new((self.bits & 1) != 0)
10    }
11}
12#[cfg(feature = "impl-register-debug")]
13impl core::fmt::Debug for R {
14    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
15        f.debug_struct("INT_ST")
16            .field("underrun", &format_args!("{}", self.underrun().bit()))
17            .finish()
18    }
19}
20#[cfg(feature = "impl-register-debug")]
21impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
22    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
23        core::fmt::Debug::fmt(&self.read(), f)
24    }
25}
26#[doc = "dsi_bridge masked interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27pub struct INT_ST_SPEC;
28impl crate::RegisterSpec for INT_ST_SPEC {
29    type Ux = u32;
30}
31#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
32impl crate::Readable for INT_ST_SPEC {}
33#[doc = "`reset()` method sets INT_ST to value 0"]
34impl crate::Resettable for INT_ST_SPEC {
35    const RESET_VALUE: u32 = 0;
36}
esp32p4/mipi_dsi_bridge/int_st.rs

esp32p4/mipi_dsi_bridge/
int_st.rs
