esp32p4/mipi_dsi_bridge/
dma_frame_interval.rs

1#[doc = "Register `DMA_FRAME_INTERVAL` reader"]
2pub type R = crate::R<DMA_FRAME_INTERVAL_SPEC>;
3#[doc = "Register `DMA_FRAME_INTERVAL` writer"]
4pub type W = crate::W<DMA_FRAME_INTERVAL_SPEC>;
5#[doc = "Field `DMA_FRAME_SLOT` reader - this field configures the max frame_slot_cnt"]
6pub type DMA_FRAME_SLOT_R = crate::FieldReader<u16>;
7#[doc = "Field `DMA_FRAME_SLOT` writer - this field configures the max frame_slot_cnt"]
8pub type DMA_FRAME_SLOT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
9#[doc = "Field `DMA_FRAME_INTERVAL` reader - this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1 when frame_slot_cnt if full"]
10pub type DMA_FRAME_INTERVAL_R = crate::FieldReader<u32>;
11#[doc = "Field `DMA_FRAME_INTERVAL` writer - this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1 when frame_slot_cnt if full"]
12pub type DMA_FRAME_INTERVAL_W<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>;
13#[doc = "Field `DMA_MULTIBLK_EN` reader - this bit configures enable multi-blk transfer, 0: disable, 1: enable"]
14pub type DMA_MULTIBLK_EN_R = crate::BitReader;
15#[doc = "Field `DMA_MULTIBLK_EN` writer - this bit configures enable multi-blk transfer, 0: disable, 1: enable"]
16pub type DMA_MULTIBLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `EN` reader - this bit configures enable interval between frame transfer, 0: disable, 1: enable"]
18pub type EN_R = crate::BitReader;
19#[doc = "Field `EN` writer - this bit configures enable interval between frame transfer, 0: disable, 1: enable"]
20pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bits 0:9 - this field configures the max frame_slot_cnt"]
23    #[inline(always)]
24    pub fn dma_frame_slot(&self) -> DMA_FRAME_SLOT_R {
25        DMA_FRAME_SLOT_R::new((self.bits & 0x03ff) as u16)
26    }
27    #[doc = "Bits 10:27 - this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1 when frame_slot_cnt if full"]
28    #[inline(always)]
29    pub fn dma_frame_interval(&self) -> DMA_FRAME_INTERVAL_R {
30        DMA_FRAME_INTERVAL_R::new((self.bits >> 10) & 0x0003_ffff)
31    }
32    #[doc = "Bit 28 - this bit configures enable multi-blk transfer, 0: disable, 1: enable"]
33    #[inline(always)]
34    pub fn dma_multiblk_en(&self) -> DMA_MULTIBLK_EN_R {
35        DMA_MULTIBLK_EN_R::new(((self.bits >> 28) & 1) != 0)
36    }
37    #[doc = "Bit 29 - this bit configures enable interval between frame transfer, 0: disable, 1: enable"]
38    #[inline(always)]
39    pub fn en(&self) -> EN_R {
40        EN_R::new(((self.bits >> 29) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("DMA_FRAME_INTERVAL")
47            .field(
48                "dma_frame_slot",
49                &format_args!("{}", self.dma_frame_slot().bits()),
50            )
51            .field(
52                "dma_frame_interval",
53                &format_args!("{}", self.dma_frame_interval().bits()),
54            )
55            .field(
56                "dma_multiblk_en",
57                &format_args!("{}", self.dma_multiblk_en().bit()),
58            )
59            .field("en", &format_args!("{}", self.en().bit()))
60            .finish()
61    }
62}
63#[cfg(feature = "impl-register-debug")]
64impl core::fmt::Debug for crate::generic::Reg<DMA_FRAME_INTERVAL_SPEC> {
65    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
66        core::fmt::Debug::fmt(&self.read(), f)
67    }
68}
69impl W {
70    #[doc = "Bits 0:9 - this field configures the max frame_slot_cnt"]
71    #[inline(always)]
72    #[must_use]
73    pub fn dma_frame_slot(&mut self) -> DMA_FRAME_SLOT_W<DMA_FRAME_INTERVAL_SPEC> {
74        DMA_FRAME_SLOT_W::new(self, 0)
75    }
76    #[doc = "Bits 10:27 - this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1 when frame_slot_cnt if full"]
77    #[inline(always)]
78    #[must_use]
79    pub fn dma_frame_interval(&mut self) -> DMA_FRAME_INTERVAL_W<DMA_FRAME_INTERVAL_SPEC> {
80        DMA_FRAME_INTERVAL_W::new(self, 10)
81    }
82    #[doc = "Bit 28 - this bit configures enable multi-blk transfer, 0: disable, 1: enable"]
83    #[inline(always)]
84    #[must_use]
85    pub fn dma_multiblk_en(&mut self) -> DMA_MULTIBLK_EN_W<DMA_FRAME_INTERVAL_SPEC> {
86        DMA_MULTIBLK_EN_W::new(self, 28)
87    }
88    #[doc = "Bit 29 - this bit configures enable interval between frame transfer, 0: disable, 1: enable"]
89    #[inline(always)]
90    #[must_use]
91    pub fn en(&mut self) -> EN_W<DMA_FRAME_INTERVAL_SPEC> {
92        EN_W::new(self, 29)
93    }
94}
95#[doc = "dsi_bridge dam frame interval control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_frame_interval::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_frame_interval::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
96pub struct DMA_FRAME_INTERVAL_SPEC;
97impl crate::RegisterSpec for DMA_FRAME_INTERVAL_SPEC {
98    type Ux = u32;
99}
100#[doc = "`read()` method returns [`dma_frame_interval::R`](R) reader structure"]
101impl crate::Readable for DMA_FRAME_INTERVAL_SPEC {}
102#[doc = "`write(|w| ..)` method takes [`dma_frame_interval::W`](W) writer structure"]
103impl crate::Writable for DMA_FRAME_INTERVAL_SPEC {
104    type Safety = crate::Unsafe;
105    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
106    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
107}
108#[doc = "`reset()` method sets DMA_FRAME_INTERVAL to value 0x2000_2409"]
109impl crate::Resettable for DMA_FRAME_INTERVAL_SPEC {
110    const RESET_VALUE: u32 = 0x2000_2409;
111}
esp32p4/mipi_dsi_bridge/dma_frame_interval.rs

esp32p4/mipi_dsi_bridge/
dma_frame_interval.rs
