esp32p4/mcpwm0/ch/
dt_cfg.rs1#[doc = "Register `DT_CFG` reader"]
2pub type R = crate::R<DT_CFG_SPEC>;
3#[doc = "Register `DT_CFG` writer"]
4pub type W = crate::W<DT_CFG_SPEC>;
5#[doc = "Field `FED_UPMETHOD` reader - Configures update method for FED (Falling edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"]
6pub type FED_UPMETHOD_R = crate::FieldReader;
7#[doc = "Field `FED_UPMETHOD` writer - Configures update method for FED (Falling edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"]
8pub type FED_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `RED_UPMETHOD` reader - Configures update method for RED (rising edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"]
10pub type RED_UPMETHOD_R = crate::FieldReader;
11#[doc = "Field `RED_UPMETHOD` writer - Configures update method for RED (rising edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"]
12pub type RED_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13#[doc = "Field `DEB_MODE` reader - Configures S8 in table, dual-edge B mode.\\\\0: fed/red take effect on different path separately\\\\1: fed/red take effect on B path, A out is in bypass or dulpB mode"]
14pub type DEB_MODE_R = crate::BitReader;
15#[doc = "Field `DEB_MODE` writer - Configures S8 in table, dual-edge B mode.\\\\0: fed/red take effect on different path separately\\\\1: fed/red take effect on B path, A out is in bypass or dulpB mode"]
16pub type DEB_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `A_OUTSWAP` reader - Configures S6 in table."]
18pub type A_OUTSWAP_R = crate::BitReader;
19#[doc = "Field `A_OUTSWAP` writer - Configures S6 in table."]
20pub type A_OUTSWAP_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `B_OUTSWAP` reader - Configures S7 in table."]
22pub type B_OUTSWAP_R = crate::BitReader;
23#[doc = "Field `B_OUTSWAP` writer - Configures S7 in table."]
24pub type B_OUTSWAP_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `RED_INSEL` reader - Configures S4 in table."]
26pub type RED_INSEL_R = crate::BitReader;
27#[doc = "Field `RED_INSEL` writer - Configures S4 in table."]
28pub type RED_INSEL_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `FED_INSEL` reader - Configures S5 in table."]
30pub type FED_INSEL_R = crate::BitReader;
31#[doc = "Field `FED_INSEL` writer - Configures S5 in table."]
32pub type FED_INSEL_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `RED_OUTINVERT` reader - Configures S2 in table."]
34pub type RED_OUTINVERT_R = crate::BitReader;
35#[doc = "Field `RED_OUTINVERT` writer - Configures S2 in table."]
36pub type RED_OUTINVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `FED_OUTINVERT` reader - Configures S3 in table."]
38pub type FED_OUTINVERT_R = crate::BitReader;
39#[doc = "Field `FED_OUTINVERT` writer - Configures S3 in table."]
40pub type FED_OUTINVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `A_OUTBYPASS` reader - Configures S1 in table."]
42pub type A_OUTBYPASS_R = crate::BitReader;
43#[doc = "Field `A_OUTBYPASS` writer - Configures S1 in table."]
44pub type A_OUTBYPASS_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `B_OUTBYPASS` reader - Configures S0 in table."]
46pub type B_OUTBYPASS_R = crate::BitReader;
47#[doc = "Field `B_OUTBYPASS` writer - Configures S0 in table."]
48pub type B_OUTBYPASS_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `CLK_SEL` reader - Configures dead time generator %s clock selection.\\\\0: PWM_clk\\\\1: PT_clk"]
50pub type CLK_SEL_R = crate::BitReader;
51#[doc = "Field `CLK_SEL` writer - Configures dead time generator %s clock selection.\\\\0: PWM_clk\\\\1: PT_clk"]
52pub type CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
53impl R {
54 #[doc = "Bits 0:3 - Configures update method for FED (Falling edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"]
55 #[inline(always)]
56 pub fn fed_upmethod(&self) -> FED_UPMETHOD_R {
57 FED_UPMETHOD_R::new((self.bits & 0x0f) as u8)
58 }
59 #[doc = "Bits 4:7 - Configures update method for RED (rising edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"]
60 #[inline(always)]
61 pub fn red_upmethod(&self) -> RED_UPMETHOD_R {
62 RED_UPMETHOD_R::new(((self.bits >> 4) & 0x0f) as u8)
63 }
64 #[doc = "Bit 8 - Configures S8 in table, dual-edge B mode.\\\\0: fed/red take effect on different path separately\\\\1: fed/red take effect on B path, A out is in bypass or dulpB mode"]
65 #[inline(always)]
66 pub fn deb_mode(&self) -> DEB_MODE_R {
67 DEB_MODE_R::new(((self.bits >> 8) & 1) != 0)
68 }
69 #[doc = "Bit 9 - Configures S6 in table."]
70 #[inline(always)]
71 pub fn a_outswap(&self) -> A_OUTSWAP_R {
72 A_OUTSWAP_R::new(((self.bits >> 9) & 1) != 0)
73 }
74 #[doc = "Bit 10 - Configures S7 in table."]
75 #[inline(always)]
76 pub fn b_outswap(&self) -> B_OUTSWAP_R {
77 B_OUTSWAP_R::new(((self.bits >> 10) & 1) != 0)
78 }
79 #[doc = "Bit 11 - Configures S4 in table."]
80 #[inline(always)]
81 pub fn red_insel(&self) -> RED_INSEL_R {
82 RED_INSEL_R::new(((self.bits >> 11) & 1) != 0)
83 }
84 #[doc = "Bit 12 - Configures S5 in table."]
85 #[inline(always)]
86 pub fn fed_insel(&self) -> FED_INSEL_R {
87 FED_INSEL_R::new(((self.bits >> 12) & 1) != 0)
88 }
89 #[doc = "Bit 13 - Configures S2 in table."]
90 #[inline(always)]
91 pub fn red_outinvert(&self) -> RED_OUTINVERT_R {
92 RED_OUTINVERT_R::new(((self.bits >> 13) & 1) != 0)
93 }
94 #[doc = "Bit 14 - Configures S3 in table."]
95 #[inline(always)]
96 pub fn fed_outinvert(&self) -> FED_OUTINVERT_R {
97 FED_OUTINVERT_R::new(((self.bits >> 14) & 1) != 0)
98 }
99 #[doc = "Bit 15 - Configures S1 in table."]
100 #[inline(always)]
101 pub fn a_outbypass(&self) -> A_OUTBYPASS_R {
102 A_OUTBYPASS_R::new(((self.bits >> 15) & 1) != 0)
103 }
104 #[doc = "Bit 16 - Configures S0 in table."]
105 #[inline(always)]
106 pub fn b_outbypass(&self) -> B_OUTBYPASS_R {
107 B_OUTBYPASS_R::new(((self.bits >> 16) & 1) != 0)
108 }
109 #[doc = "Bit 17 - Configures dead time generator %s clock selection.\\\\0: PWM_clk\\\\1: PT_clk"]
110 #[inline(always)]
111 pub fn clk_sel(&self) -> CLK_SEL_R {
112 CLK_SEL_R::new(((self.bits >> 17) & 1) != 0)
113 }
114}
115#[cfg(feature = "impl-register-debug")]
116impl core::fmt::Debug for R {
117 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
118 f.debug_struct("DT_CFG")
119 .field(
120 "fed_upmethod",
121 &format_args!("{}", self.fed_upmethod().bits()),
122 )
123 .field(
124 "red_upmethod",
125 &format_args!("{}", self.red_upmethod().bits()),
126 )
127 .field("deb_mode", &format_args!("{}", self.deb_mode().bit()))
128 .field("a_outswap", &format_args!("{}", self.a_outswap().bit()))
129 .field("b_outswap", &format_args!("{}", self.b_outswap().bit()))
130 .field("red_insel", &format_args!("{}", self.red_insel().bit()))
131 .field("fed_insel", &format_args!("{}", self.fed_insel().bit()))
132 .field(
133 "red_outinvert",
134 &format_args!("{}", self.red_outinvert().bit()),
135 )
136 .field(
137 "fed_outinvert",
138 &format_args!("{}", self.fed_outinvert().bit()),
139 )
140 .field("a_outbypass", &format_args!("{}", self.a_outbypass().bit()))
141 .field("b_outbypass", &format_args!("{}", self.b_outbypass().bit()))
142 .field("clk_sel", &format_args!("{}", self.clk_sel().bit()))
143 .finish()
144 }
145}
146#[cfg(feature = "impl-register-debug")]
147impl core::fmt::Debug for crate::generic::Reg<DT_CFG_SPEC> {
148 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
149 core::fmt::Debug::fmt(&self.read(), f)
150 }
151}
152impl W {
153 #[doc = "Bits 0:3 - Configures update method for FED (Falling edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"]
154 #[inline(always)]
155 #[must_use]
156 pub fn fed_upmethod(&mut self) -> FED_UPMETHOD_W<DT_CFG_SPEC> {
157 FED_UPMETHOD_W::new(self, 0)
158 }
159 #[doc = "Bits 4:7 - Configures update method for RED (rising edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"]
160 #[inline(always)]
161 #[must_use]
162 pub fn red_upmethod(&mut self) -> RED_UPMETHOD_W<DT_CFG_SPEC> {
163 RED_UPMETHOD_W::new(self, 4)
164 }
165 #[doc = "Bit 8 - Configures S8 in table, dual-edge B mode.\\\\0: fed/red take effect on different path separately\\\\1: fed/red take effect on B path, A out is in bypass or dulpB mode"]
166 #[inline(always)]
167 #[must_use]
168 pub fn deb_mode(&mut self) -> DEB_MODE_W<DT_CFG_SPEC> {
169 DEB_MODE_W::new(self, 8)
170 }
171 #[doc = "Bit 9 - Configures S6 in table."]
172 #[inline(always)]
173 #[must_use]
174 pub fn a_outswap(&mut self) -> A_OUTSWAP_W<DT_CFG_SPEC> {
175 A_OUTSWAP_W::new(self, 9)
176 }
177 #[doc = "Bit 10 - Configures S7 in table."]
178 #[inline(always)]
179 #[must_use]
180 pub fn b_outswap(&mut self) -> B_OUTSWAP_W<DT_CFG_SPEC> {
181 B_OUTSWAP_W::new(self, 10)
182 }
183 #[doc = "Bit 11 - Configures S4 in table."]
184 #[inline(always)]
185 #[must_use]
186 pub fn red_insel(&mut self) -> RED_INSEL_W<DT_CFG_SPEC> {
187 RED_INSEL_W::new(self, 11)
188 }
189 #[doc = "Bit 12 - Configures S5 in table."]
190 #[inline(always)]
191 #[must_use]
192 pub fn fed_insel(&mut self) -> FED_INSEL_W<DT_CFG_SPEC> {
193 FED_INSEL_W::new(self, 12)
194 }
195 #[doc = "Bit 13 - Configures S2 in table."]
196 #[inline(always)]
197 #[must_use]
198 pub fn red_outinvert(&mut self) -> RED_OUTINVERT_W<DT_CFG_SPEC> {
199 RED_OUTINVERT_W::new(self, 13)
200 }
201 #[doc = "Bit 14 - Configures S3 in table."]
202 #[inline(always)]
203 #[must_use]
204 pub fn fed_outinvert(&mut self) -> FED_OUTINVERT_W<DT_CFG_SPEC> {
205 FED_OUTINVERT_W::new(self, 14)
206 }
207 #[doc = "Bit 15 - Configures S1 in table."]
208 #[inline(always)]
209 #[must_use]
210 pub fn a_outbypass(&mut self) -> A_OUTBYPASS_W<DT_CFG_SPEC> {
211 A_OUTBYPASS_W::new(self, 15)
212 }
213 #[doc = "Bit 16 - Configures S0 in table."]
214 #[inline(always)]
215 #[must_use]
216 pub fn b_outbypass(&mut self) -> B_OUTBYPASS_W<DT_CFG_SPEC> {
217 B_OUTBYPASS_W::new(self, 16)
218 }
219 #[doc = "Bit 17 - Configures dead time generator %s clock selection.\\\\0: PWM_clk\\\\1: PT_clk"]
220 #[inline(always)]
221 #[must_use]
222 pub fn clk_sel(&mut self) -> CLK_SEL_W<DT_CFG_SPEC> {
223 CLK_SEL_W::new(self, 17)
224 }
225}
226#[doc = "Dead time configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dt_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dt_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
227pub struct DT_CFG_SPEC;
228impl crate::RegisterSpec for DT_CFG_SPEC {
229 type Ux = u32;
230}
231#[doc = "`read()` method returns [`dt_cfg::R`](R) reader structure"]
232impl crate::Readable for DT_CFG_SPEC {}
233#[doc = "`write(|w| ..)` method takes [`dt_cfg::W`](W) writer structure"]
234impl crate::Writable for DT_CFG_SPEC {
235 type Safety = crate::Unsafe;
236 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
237 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
238}
239#[doc = "`reset()` method sets DT_CFG to value 0x0001_8000"]
240impl crate::Resettable for DT_CFG_SPEC {
241 const RESET_VALUE: u32 = 0x0001_8000;
242}