esp32p4/mcpwm0/
cap_timer_cfg.rs

1#[doc = "Register `CAP_TIMER_CFG` reader"]
2pub type R = crate::R<CAP_TIMER_CFG_SPEC>;
3#[doc = "Register `CAP_TIMER_CFG` writer"]
4pub type W = crate::W<CAP_TIMER_CFG_SPEC>;
5#[doc = "Field `CAP_TIMER_EN` reader - Configures whether or not to enable capture timer increment.\\\\0: Disable\\\\1: Enable"]
6pub type CAP_TIMER_EN_R = crate::BitReader;
7#[doc = "Field `CAP_TIMER_EN` writer - Configures whether or not to enable capture timer increment.\\\\0: Disable\\\\1: Enable"]
8pub type CAP_TIMER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CAP_SYNCI_EN` reader - Configures whether or not to enable capture timer sync.\\\\0: Disable\\\\1: Enable"]
10pub type CAP_SYNCI_EN_R = crate::BitReader;
11#[doc = "Field `CAP_SYNCI_EN` writer - Configures whether or not to enable capture timer sync.\\\\0: Disable\\\\1: Enable"]
12pub type CAP_SYNCI_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CAP_SYNCI_SEL` reader - Configures the selection of capture module sync input.\\\\0: None\\\\1: Timer0 sync_out\\\\2: Timer1 sync_out\\\\3: Timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\7: None"]
14pub type CAP_SYNCI_SEL_R = crate::FieldReader;
15#[doc = "Field `CAP_SYNCI_SEL` writer - Configures the selection of capture module sync input.\\\\0: None\\\\1: Timer0 sync_out\\\\2: Timer1 sync_out\\\\3: Timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\7: None"]
16pub type CAP_SYNCI_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17#[doc = "Field `CAP_SYNC_SW` writer - Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\\\0: Invalid, No effect\\\\1: Trigger a capture timer sync, capture timer is loaded with value in phase register"]
18pub type CAP_SYNC_SW_W<'a, REG> = crate::BitWriter<'a, REG>;
19impl R {
20    #[doc = "Bit 0 - Configures whether or not to enable capture timer increment.\\\\0: Disable\\\\1: Enable"]
21    #[inline(always)]
22    pub fn cap_timer_en(&self) -> CAP_TIMER_EN_R {
23        CAP_TIMER_EN_R::new((self.bits & 1) != 0)
24    }
25    #[doc = "Bit 1 - Configures whether or not to enable capture timer sync.\\\\0: Disable\\\\1: Enable"]
26    #[inline(always)]
27    pub fn cap_synci_en(&self) -> CAP_SYNCI_EN_R {
28        CAP_SYNCI_EN_R::new(((self.bits >> 1) & 1) != 0)
29    }
30    #[doc = "Bits 2:4 - Configures the selection of capture module sync input.\\\\0: None\\\\1: Timer0 sync_out\\\\2: Timer1 sync_out\\\\3: Timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\7: None"]
31    #[inline(always)]
32    pub fn cap_synci_sel(&self) -> CAP_SYNCI_SEL_R {
33        CAP_SYNCI_SEL_R::new(((self.bits >> 2) & 7) as u8)
34    }
35}
36#[cfg(feature = "impl-register-debug")]
37impl core::fmt::Debug for R {
38    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
39        f.debug_struct("CAP_TIMER_CFG")
40            .field(
41                "cap_timer_en",
42                &format_args!("{}", self.cap_timer_en().bit()),
43            )
44            .field(
45                "cap_synci_en",
46                &format_args!("{}", self.cap_synci_en().bit()),
47            )
48            .field(
49                "cap_synci_sel",
50                &format_args!("{}", self.cap_synci_sel().bits()),
51            )
52            .finish()
53    }
54}
55#[cfg(feature = "impl-register-debug")]
56impl core::fmt::Debug for crate::generic::Reg<CAP_TIMER_CFG_SPEC> {
57    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
58        core::fmt::Debug::fmt(&self.read(), f)
59    }
60}
61impl W {
62    #[doc = "Bit 0 - Configures whether or not to enable capture timer increment.\\\\0: Disable\\\\1: Enable"]
63    #[inline(always)]
64    #[must_use]
65    pub fn cap_timer_en(&mut self) -> CAP_TIMER_EN_W<CAP_TIMER_CFG_SPEC> {
66        CAP_TIMER_EN_W::new(self, 0)
67    }
68    #[doc = "Bit 1 - Configures whether or not to enable capture timer sync.\\\\0: Disable\\\\1: Enable"]
69    #[inline(always)]
70    #[must_use]
71    pub fn cap_synci_en(&mut self) -> CAP_SYNCI_EN_W<CAP_TIMER_CFG_SPEC> {
72        CAP_SYNCI_EN_W::new(self, 1)
73    }
74    #[doc = "Bits 2:4 - Configures the selection of capture module sync input.\\\\0: None\\\\1: Timer0 sync_out\\\\2: Timer1 sync_out\\\\3: Timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\7: None"]
75    #[inline(always)]
76    #[must_use]
77    pub fn cap_synci_sel(&mut self) -> CAP_SYNCI_SEL_W<CAP_TIMER_CFG_SPEC> {
78        CAP_SYNCI_SEL_W::new(self, 2)
79    }
80    #[doc = "Bit 5 - Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\\\0: Invalid, No effect\\\\1: Trigger a capture timer sync, capture timer is loaded with value in phase register"]
81    #[inline(always)]
82    #[must_use]
83    pub fn cap_sync_sw(&mut self) -> CAP_SYNC_SW_W<CAP_TIMER_CFG_SPEC> {
84        CAP_SYNC_SW_W::new(self, 5)
85    }
86}
87#[doc = "Capture timer configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cap_timer_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cap_timer_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
88pub struct CAP_TIMER_CFG_SPEC;
89impl crate::RegisterSpec for CAP_TIMER_CFG_SPEC {
90    type Ux = u32;
91}
92#[doc = "`read()` method returns [`cap_timer_cfg::R`](R) reader structure"]
93impl crate::Readable for CAP_TIMER_CFG_SPEC {}
94#[doc = "`write(|w| ..)` method takes [`cap_timer_cfg::W`](W) writer structure"]
95impl crate::Writable for CAP_TIMER_CFG_SPEC {
96    type Safety = crate::Unsafe;
97    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
98    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
99}
100#[doc = "`reset()` method sets CAP_TIMER_CFG to value 0"]
101impl crate::Resettable for CAP_TIMER_CFG_SPEC {
102    const RESET_VALUE: u32 = 0;
103}
esp32p4/mcpwm0/cap_timer_cfg.rs

esp32p4/mcpwm0/
cap_timer_cfg.rs
