esp32p4/lp_tsens/
int_ena_w1tc.rs

1#[doc = "Register `INT_ENA_W1TC` writer"]
2pub type W = crate::W<INT_ENA_W1TC_SPEC>;
3#[doc = "Field `COCPU_TSENS_WAKE_INT_ENA_W1TC` writer - Write 1 to this field to deassert interrupt enable."]
4pub type COCPU_TSENS_WAKE_INT_ENA_W1TC_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[cfg(feature = "impl-register-debug")]
6impl core::fmt::Debug for crate::generic::Reg<INT_ENA_W1TC_SPEC> {
7    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
8        write!(f, "(not readable)")
9    }
10}
11impl W {
12    #[doc = "Bit 0 - Write 1 to this field to deassert interrupt enable."]
13    #[inline(always)]
14    #[must_use]
15    pub fn cocpu_tsens_wake_int_ena_w1tc(
16        &mut self,
17    ) -> COCPU_TSENS_WAKE_INT_ENA_W1TC_W<INT_ENA_W1TC_SPEC> {
18        COCPU_TSENS_WAKE_INT_ENA_W1TC_W::new(self, 0)
19    }
20}
21#[doc = "Tsens wakeup interrupt enable deassert.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22pub struct INT_ENA_W1TC_SPEC;
23impl crate::RegisterSpec for INT_ENA_W1TC_SPEC {
24    type Ux = u32;
25}
26#[doc = "`write(|w| ..)` method takes [`int_ena_w1tc::W`](W) writer structure"]
27impl crate::Writable for INT_ENA_W1TC_SPEC {
28    type Safety = crate::Unsafe;
29    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
30    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
31}
32#[doc = "`reset()` method sets INT_ENA_W1TC to value 0"]
33impl crate::Resettable for INT_ENA_W1TC_SPEC {
34    const RESET_VALUE: u32 = 0;
35}
esp32p4/lp_tsens/int_ena_w1tc.rs

esp32p4/lp_tsens/
int_ena_w1tc.rs
